| 2007 |
|---|
| 7 | EE | Satoshi Shigematsu,
Hiroki Morimura,
Toshishige Shimamura,
Takahiro Hatano,
Namiko Ikeda,
Yukio Okazaki,
Katsuyuki Machida,
Mamoru Nakanishi:
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.
IEICE Transactions 90-C(10): 1892-1899 (2007) |
| 2006 |
|---|
| 6 | EE | Satoshi Shigematsu,
Koji Fujii,
Hiroki Morimura,
Takahiro Hatano,
Mamoru Nakanishi,
Namiko Ikeda,
Toshishige Shimamura,
Katsuyuki Machida,
Yukio Okazaki,
Hakaru Kyuragi:
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Transactions 89-C(4): 540-550 (2006) |
| 2005 |
|---|
| 5 | EE | Satoshi Shigematsu,
Hiroki Morimura,
Katsuyuki Machida,
Yukio Okazaki,
Hakaru Kyuragi:
Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Transactions 88-C(5): 1070-1078 (2005) |
| 2002 |
|---|
| 4 | EE | Namiko Ikeda,
Mamoru Nakanishi,
Koji Fujii,
Takahiro Hatano,
Satoshi Shigematsu,
Takuya Adachi,
Yukio Okazaki,
Hakaru Kyuragi:
Fingerprint Image Enhancement by Pixel-Parallel Processing.
ICPR (3) 2002: 752-755 |
| 3 | EE | Takahiro Hatano,
Takuya Adachi,
Satoshi Shigematsu,
Hiroki Morimura,
Shigehiko Onishi,
Yukio Okazaki,
Hakaru Kyuragi:
A Fingerprint Verification Algorithm Using the Differential Matching Rate.
ICPR (3) 2002: 799-802 |
| 1999 |
|---|
| 2 | EE | Shinichiro Mutoh,
Satoshi Shigematsu,
Yoshinori Gotoh,
Shinsuke Konaka:
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs.
ASP-DAC 1999: 113-116 |
| 1 | EE | Hiroki Morimura,
Satoshi Shigematsu,
Shinsuke Konaka:
A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.
ISLPED 1999: 12-17 |
