| |
| 1999 | ||
|---|---|---|
| 4 | EE | Hidehisa Nagano, Takayuki Suyama, Akira Nagoya: Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. ASP-DAC 1999: 161-164 |
| 3 | EE | Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya: A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. FPGA 1999: 251 |
| 2 | Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya: An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture. IPPS/SPDP Workshops 1999: 670-678 | |
| 1998 | ||
| 1 | EE | Hidehisa Nagano, Takayuki Suyama, Akira Nagoya: Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). FPGA 1998: 261 |
| 1 | Akihiro Matsuura | [2] [3] |
| 2 | Akira Nagoya | [1] [2] [3] [4] |
| 3 | Takayuki Suyama | [1] [4] |