| 2009 |
|---|
| 133 | EE | Yale N. Patt:
The Challenges of Multicore: Information and Mis-Information.
ARCS 2009: 3 |
| 132 | EE | M. Aater Suleman,
Onur Mutlu,
Moinuddin K. Qureshi,
Yale N. Patt:
Accelerating critical section execution with asymmetric multi-core architectures.
ASPLOS 2009: 253-264 |
| 131 | EE | Eiman Ebrahimi,
Onur Mutlu,
Yale N. Patt:
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems.
HPCA 2009: 7-17 |
| 130 | EE | Yale N. Patt:
Multi-core demands multi-interfaces.
PPOPP 2009: 99-100 |
| 2008 |
|---|
| 129 | EE | M. Aater Suleman,
Moinuddin K. Qureshi,
Yale N. Patt:
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs.
ASPLOS 2008: 277-286 |
| 128 | EE | José A. Joao,
Onur Mutlu,
Hyesoon Kim,
Rishi Agarwal,
Yale N. Patt:
Improving the performance of object-oriented languages with dynamic predication of indirect jumps.
ASPLOS 2008: 80-90 |
| 127 | EE | Chang Joo Lee,
Hyesoon Kim,
Onur Mutlu,
Yale N. Patt:
Performance-aware speculation control using wrong path usefulness prediction.
HPCA 2008: 39-49 |
| 126 | EE | Francis Tseng,
Yale N. Patt:
Achieving Out-of-Order Performance with Almost In-Order Complexity.
ISCA 2008: 3-12 |
| 125 | EE | Chang Joo Lee,
Onur Mutlu,
Veynu Narasiman,
Yale N. Patt:
Prefetch-Aware DRAM Controllers.
MICRO 2008: 200-209 |
| 124 | EE | Yale N. Patt:
Can They Be Fixed: Some Thoughts After 40 Years in the Business.
SAMOS 2008: 1 |
| 123 | EE | Moinuddin K. Qureshi,
Aamer Jaleel,
Yale N. Patt,
Simon C. Steely Jr.,
Joel S. Emer:
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching.
IEEE Micro 28(1): 91-98 (2008) |
| 2007 |
|---|
| 122 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Yale N. Patt:
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors.
CGO 2007: 367-378 |
| 121 | EE | Moinuddin K. Qureshi,
M. Aater Suleman,
Yale N. Patt:
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines.
HPCA 2007: 250-259 |
| 120 | EE | Santhosh Srinath,
Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers.
HPCA 2007: 63-74 |
| 119 | EE | Yale N. Patt:
The Transformation Hierarchy in the Era of Multi-core.
HiPC 2007: 5 |
| 118 | EE | Moinuddin K. Qureshi,
Aamer Jaleel,
Yale N. Patt,
Simon C. Steely Jr.,
Joel S. Emer:
Adaptive insertion policies for high performance caching.
ISCA 2007: 381-391 |
| 117 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Chang Joo Lee,
Yale N. Patt,
Robert Cohn:
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.
ISCA 2007: 424-435 |
| 116 | EE | José A. Joao,
Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Dynamic Predication of Indirect Jumps.
Computer Architecture Letters 6(2): 25-28 (2007) |
| 115 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Yale N. Patt:
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication.
IEEE Micro 27(1): 94-104 (2007) |
| 114 | EE | Joel S. Emer,
Mark D. Hill,
Yale N. Patt,
Joshua J. Yi,
Derek Chiou,
Resit Sendag:
Single-Threaded vs. Multithreaded: Where Should We Focus?
IEEE Micro 27(6): 14-24 (2007) |
| 2006 |
|---|
| 113 | EE | Hyesoon Kim,
M. Aater Suleman,
Onur Mutlu,
Yale N. Patt:
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set.
CGO 2006: 159-172 |
| 112 | EE | Moinuddin K. Qureshi,
Daniel N. Lynch,
Onur Mutlu,
Yale N. Patt:
A Case for MLP-Aware Cache Replacement.
ISCA 2006: 167-178 |
| 111 | EE | Yale N. Patt:
Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?
ISCA 2006: 2 |
| 110 | EE | Moinuddin K. Qureshi,
Yale N. Patt:
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches.
MICRO 2006: 423-432 |
| 109 | EE | Hyesoon Kim,
José A. Joao,
Onur Mutlu,
Yale N. Patt:
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.
MICRO 2006: 53-64 |
| 108 | EE | Jean-Luc Gaudiot,
Yale N. Patt,
Kevin Skadron:
Foreword.
Computer Architecture Letters 5(2): (2006) |
| 107 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance.
IEEE Micro 26(1): 10-20 (2006) |
| 106 | EE | Hyesoon Kim,
Onur Mutlu,
Yale N. Patt,
Jared Stark:
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution.
IEEE Micro 26(1): 48-58 (2006) |
| 105 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.
IEEE Trans. Computers 55(12): 1491-1508 (2006) |
| 2005 |
|---|
| 104 | EE | Yale N. Patt:
The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints?
AICCSA 2005: 1 |
| 103 | EE | Moinuddin K. Qureshi,
Onur Mutlu,
Yale N. Patt:
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.
DSN 2005: 434-443 |
| 102 | EE | Yale N. Patt:
A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox).
IPDPS 2005 |
| 101 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Techniques for Efficient Processing in Runahead Execution Engines.
ISCA 2005: 370-381 |
| 100 | EE | Moinuddin K. Qureshi,
David Thompson,
Yale N. Patt:
The V-Way Cache: Demand Based Associativity via Global Replacement.
ISCA 2005: 544-555 |
| 99 | EE | Onur Mutlu,
Hyesoon Kim,
Yale N. Patt:
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns.
MICRO 2005: 233-244 |
| 98 | EE | Hyesoon Kim,
Onur Mutlu,
Jared Stark,
Yale N. Patt:
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.
MICRO 2005: 43-54 |
| 97 | EE | Onur Mutlu,
Hyesoon Kim,
Jared Stark,
Yale N. Patt:
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.
Computer Architecture Letters 4(1): 2 (2005) |
| 96 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.
IEEE Trans. Computers 54(12): 1556-1571 (2005) |
| 95 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.
International Journal of Parallel Programming 33(5): 529-559 (2005) |
| 2004 |
|---|
| 94 | EE | Yale N. Patt:
Opening and keynote 1.
ISPASS 2004: 1 |
| 93 | EE | Brad Calder,
Daniel Citron,
Yale N. Patt,
James E. Smith:
The future of simulation: A field of dreams.
ISPASS 2004: 169 |
| 92 | EE | David N. Armstrong,
Hyesoon Kim,
Onur Mutlu,
Yale N. Patt:
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery.
MICRO 2004: 119-128 |
| 91 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance.
SBAC-PAD 2004: 2-9 |
| 90 | EE | Onur Mutlu,
Hyesoon Kim,
David N. Armstrong,
Yale N. Patt:
Understanding the effects of wrong-path memory references on processor performance.
WMPI 2004: 56-64 |
| 2003 |
|---|
| 89 | EE | Onur Mutlu,
Jared Stark,
Chris Wilkerson,
Yale N. Patt:
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.
HPCA 2003: 129-140 |
| 88 | EE | Yale N. Patt:
The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like?
HiPC 2003: 105 |
| 87 | EE | Paul Racunas,
Yale N. Patt:
Partitioned first-level cache design for clustered microarchitectures.
ICS 2003: 22-31 |
| 86 | EE | Onur Mutlu,
Jared Stark,
Chris Wilkerson,
Yale N. Patt:
Runahead Execution: An Effective Alternative to Large Instruction Windows.
IEEE Micro 23(6): 20-25 (2003) |
| 2002 |
|---|
| 85 | EE | Stephen W. Melvin,
Yale N. Patt:
Handling of packet dependencies: a critical issue for highly parallel network processors.
CASES 2002: 202-209 |
| 84 | EE | Mary D. Brown,
Yale N. Patt:
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.
HPCA 2002: 289-298 |
| 83 | EE | Robert S. Chappell,
Francis Tseng,
Yale N. Patt,
Adi Yoaz:
Difficult-Path Branch Prediction Using Subordinate Microthreads.
ISCA 2002: 307-317 |
| 82 | EE | Robert S. Chappell,
Francis Tseng,
Adi Yoaz,
Yale N. Patt:
Microarchitectural support for precomputation microthreads.
MICRO 2002: 74-84 |
| 2001 |
|---|
| 81 | EE | Mary D. Brown,
Jared Stark,
Yale N. Patt:
Select-free instruction scheduling logic.
MICRO 2001: 204-213 |
| 80 | EE | Judith L. Gersting,
Peter B. Henderson,
Philip Machanick,
Yale N. Patt:
Programming early considered harmful.
SIGCSE 2001: 402-403 |
| 2000 |
|---|
| 79 | EE | Yale N. Patt:
Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve?
EUROMICRO 2000: 1015 |
| 78 | EE | Jared Stark,
Mary D. Brown,
Yale N. Patt:
On pipelining dynamic instruction scheduling logic.
MICRO 2000: 57-66 |
| 77 | EE | Gregory R. Ganger,
Marshall K. McKusick,
Craig A. N. Soules,
Yale N. Patt:
Soft updates: a solution to the metadata update problem in file systems.
ACM Trans. Comput. Syst. 18(2): 127-153 (2000) |
| 1999 |
|---|
| 76 | EE | Robert S. Chappell,
Jared Stark,
Sangwook P. Kim,
Steven K. Reinhardt,
Yale N. Patt:
Simultaneous Subordinate Microthreading (SSMT).
ISCA 1999: 186-195 |
| 75 | EE | Sanjay J. Patel,
Daniel H. Friendly,
Yale N. Patt:
Evaluation of Design Options for the Trace Cache Fetch Mechanism.
IEEE Trans. Computers 48(2): 193-204 (1999) |
| 1998 |
|---|
| 74 | EE | Wen-mei W. Hwu,
Yale N. Patt:
HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality.
25 Years ISCA: Retrospectives and Reprints 1998: 300-308 |
| 73 | EE | Wen-mei W. Hwu,
Yale N. Patt:
Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality.
25 Years ISCA: Retrospectives and Reprints 1998: 43-44 |
| 72 | EE | Tse-Yu Yeh,
Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction.
25 Years ISCA: Retrospectives and Reprints 1998: 451-461 |
| 71 | EE | Tse-Yu Yeh,
Yale N. Patt:
Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction.
25 Years ISCA: Retrospectives and Reprints 1998: 87-88 |
| 70 | EE | Jared Stark,
Marius Evers,
Yale N. Patt:
Variable Length Path Branch Prediction.
ASPLOS 1998: 170-179 |
| 69 | EE | Sanjay J. Patel,
Marius Evers,
Yale N. Patt:
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.
ISCA 1998: 262-271 |
| 68 | EE | Marius Evers,
Sanjay J. Patel,
Robert S. Chappell,
Yale N. Patt:
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.
ISCA 1998: 52-61 |
| 67 | EE | Daniel H. Friendly,
Sanjay J. Patel,
Yale N. Patt:
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors.
MICRO 1998: 173-181 |
| 66 | | Gregory R. Ganger,
Yale N. Patt:
Using System-Level Models to Evaluate I/O Subsystem Designs.
IEEE Trans. Computers 47(6): 667-678 (1998) |
| 65 | | Eric Hao,
Po-Yung Chang,
Marius Evers,
Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures.
International Journal of Parallel Programming 26(4): 449-478 (1998) |
| 1997 |
|---|
| 64 | | Robert Y. Hou,
Yale N. Patt:
Using Non-Volatile Storage to Improve the Reliability of RAID5 Disk Arrays.
FTCS 1997: 206-215 |
| 63 | EE | Po-Yung Chang,
Eric Hao,
Yale N. Patt:
Target Prediction for Indirect Jumps.
ISCA 1997: 274-283 |
| 62 | EE | Eric Sprangle,
Robert S. Chappell,
Mitch Alsup,
Yale N. Patt:
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference.
ISCA 1997: 284-291 |
| 61 | EE | Daniel H. Friendly,
Sanjay J. Patel,
Yale N. Patt:
Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism.
MICRO 1997: 24-33 |
| 60 | EE | Jared Stark,
Paul Racunas,
Yale N. Patt:
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.
MICRO 1997: 34-43 |
| 59 | | Yale N. Patt:
Identifiying Obstacles in the Path to More.
IEEE Computer 30(12): 32 (1997) |
| 58 | | Yale N. Patt,
Sanjay J. Patel,
Marius Evers,
Daniel H. Friendly,
Jared Stark:
One Billion Transistors, One Uniprocessor, One Chip.
IEEE Computer 30(9): 51-57 (1997) |
| 1996 |
|---|
| 57 | EE | Marius Evers,
Po-Yung Chang,
Yale N. Patt:
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches.
ISCA 1996: 3-11 |
| 56 | EE | Eric Hao,
Po-Yung Chang,
Marius Evers,
Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures.
MICRO 1996: 191-200 |
| 55 | | Yale N. Patt:
Microarchitecture, Compilers and Algorithms.
ACM Comput. Surv. 28(4es): 33 (1996) |
| 54 | | Yale N. Patt:
First Courses and Fundamentals.
ACM Comput. Surv. 28(4es): 99 (1996) |
| 1995 |
|---|
| 53 | | Robert Y. Hou,
Yale N. Patt:
Track Piggybacking: An Improved Rebuild Algorithm for RAID5 Disk Arrays.
ICPP (1) 1995: 136-145 |
| 52 | EE | Po-Ying Chang,
Eric Hao,
Yale N. Patt:
Alternative implementations of hybrid branch predictors.
MICRO 1995: 252-257 |
| 51 | | Bruce L. Worthington,
Gregory R. Ganger,
Yale N. Patt,
John Wilkes:
On-Line Extraction of SCSI Disk Drive Parameters.
SIGMETRICS 1995: 146-156 |
| 1994 |
|---|
| 50 | EE | Eric Sprangle,
Yale N. Patt:
Facilitating superscalar processing via a combined static/dynamic register renaming scheme.
MICRO 1994: 143-147 |
| 49 | EE | Po-Yung Chang,
Eric Hao,
Tse-Yu Yeh,
Yale N. Patt:
Branch classification: a new mechanism for improving branch predictor performance.
MICRO 1994: 22-31 |
| 48 | EE | Eric Hao,
Po-Yung Chang,
Yale N. Patt:
The effect of speculatively updating branch history on branch prediction accuracy, revisited.
MICRO 1994: 228-232 |
| 47 | | Gregory R. Ganger,
Yale N. Patt:
Metadata Update Performance in File Systems.
OSDI 1994: 49-60 |
| 46 | | Bruce L. Worthington,
Gregory R. Ganger,
Yale N. Patt:
Scheduling Algorithms for Modern Disk Drives.
SIGMETRICS 1994: 241-252 |
| 45 | | Yale N. Patt:
The I/O Subsystem - A Candidate for Improvement: Guest Editor's Introduction.
IEEE Computer 27(3): 15-16 (1994) |
| 44 | | Gregory R. Ganger,
Bruce L. Worthington,
Robert Y. Hou,
Yale N. Patt:
Disk Arrays: High-Performance, High-Reliability Storage Subsystems.
IEEE Computer 27(3): 30-36 (1994) |
| 1993 |
|---|
| 43 | | Robert Y. Hou,
Yale N. Patt:
Trading Disk Capacity for Performance.
HPDC 1993: 263-270 |
| 42 | | Tse-Yu Yeh,
Yale N. Patt:
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History.
ISCA 1993: 257-266 |
| 41 | EE | Tse-Yu Yeh,
Deborah T. Marr,
Yale N. Patt:
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache.
International Conference on Supercomputing 1993: 67-76 |
| 40 | EE | Tse-Yu Yeh,
Yale N. Patt:
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors.
MICRO 1993: 164-175 |
| 39 | EE | Michael Butler,
Yale N. Patt:
A comparative performance evaluation of various state maintenance mechanisms.
MICRO 1993: 70-79 |
| 38 | | Gregory R. Ganger,
Yale N. Patt:
The Process-Flow Model: Examining I/O Performance from the System's Point of View.
SIGMETRICS 1993: 86-97 |
| 37 | EE | Robert Y. Hou,
Yale N. Patt:
Comparing Rebuild Algorithms for Mirrored and RAID5 Disk Arrays.
SIGMOD Conference 1993: 317-326 |
| 1992 |
|---|
| 36 | | Tse-Yu Yeh,
Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction.
ISCA 1992: 124-134 |
| 35 | EE | Michael Butler,
Yale N. Patt:
An investigation of the performance of various dynamic scheduling techniques.
MICRO 1992: 1-9 |
| 34 | EE | Tse-Yu Yeh,
Yale N. Patt:
A comprehensive instruction fetch mechanism for a processor supporting speculative execution.
MICRO 1992: 129-139 |
| 33 | | Howard Jay Siegel,
Seth Abraham,
William L. Bain,
Kenneth E. Batcher,
Thomas L. Casavant,
Doug DeGroot,
Jack B. Dennis,
David C. Douglas,
Tse-Yun Feng,
James R. Goodman,
Alan Huang,
Harry F. Jordan,
J. Robert Jamp,
Yale N. Patt,
Alan Jay Smith,
James E. Smith,
Lawrence Snyder,
Harold S. Stone,
Russ Tuck,
Benjamin W. Wah:
Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing.
J. Parallel Distrib. Comput. 16(3): 199-211 (1992) |
| 1991 |
|---|
| 32 | EE | Michael Butler,
Tse-Yu Yeh,
Yale N. Patt,
Mitch Alsup,
Hunter Scales,
Michael Shebanow:
Single Instruction Stream Parallelism is Greater Than Two.
ISCA 1991: 276-286 |
| 31 | EE | Stephen W. Melvin,
Yale N. Patt:
Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques.
ISCA 1991: 287-296 |
| 30 | EE | Michael Butler,
Yale N. Patt:
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling.
MICRO 1991: 34-41 |
| 29 | EE | Tse-Yu Yeh,
Yale N. Patt:
Two-Level Adaptive Training Branch Prediction.
MICRO 1991: 51-61 |
| 28 | | Yale N. Patt:
Experimental Research in Computer Architecture - Guest Editor's Introduction to the Special Issue.
IEEE Computer 24(1): 14-16 (1991) |
| 1990 |
|---|
| 27 | | Michael Butler,
Yale N. Patt:
An Area-Efficient Register Alias Table for Implementing HPS.
ICPP (1) 1990: 611-612 |
| 1989 |
|---|
| 26 | EE | Stephen W. Melvin,
Yale N. Patt:
Performance benefits of large execution atomic units in dynamically scheduled machines.
ICS 1989: 427-432 |
| 25 | EE | Ashok Singhal,
Yale N. Patt:
A High Performance Prolog Processor with Multiple Function Units.
ISCA 1989: 195-202 |
| 24 | EE | Yale N. Patt:
Microarchitecture choices (implementation of the VAX).
MICRO 1989: 213-216 |
| 23 | | Ashok Singhal,
Yale N. Patt:
Unification Parallelism: How Much Can We Exploit?
NACLP 1989: 1135-1147 |
| 22 | | Yale N. Patt:
Real Machines: Design Choices / Engineering Trade-Offs - Guest Editor's Introduction.
IEEE Computer 22(1): 8-10 (1989) |
| 1988 |
|---|
| 21 | EE | John A. Swensen,
Yale N. Patt:
Hierarchical registers for scientific computers.
ICS 1988: 346-354 |
| 20 | EE | Ashok Singhal,
Yale N. Patt:
Implementing a Prolog machine with multiple functional units.
MICRO 1988: 41-49 |
| 19 | EE | Stephen W. Melvin,
Michael Shebanow,
Yale N. Patt:
Hardware support for large atomic units in dynamically scheduled machines.
MICRO 1988: 60-63 |
| 18 | | Stephen W. Melvin,
Yale N. Patt:
The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels.
SIGMETRICS 1988: 207-214 |
| 1987 |
|---|
| 17 | | Jeff Gee,
Stephen W. Melvin,
Yale N. Patt:
Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer.
ICLP 1987: 1-20 |
| 16 | | Wen-mei W. Hwu,
Yale N. Patt:
Checkpoint Repair for Out-of-order Execution Machines.
ISCA 1987: 18-26 |
| 15 | | John A. Swensen,
Yale N. Patt:
Fast Temporary Storage for Serial and Parallel Execution.
ISCA 1987: 35-43 |
| 14 | EE | Wen-mei W. Hwu,
Yale N. Patt:
Exploiting horizontal and vertical concurrency via the HPSm microprocessor.
MICRO 1987: 154-161 |
| 13 | EE | James E. Wilson,
Stephen W. Melvin,
Michael Shebanow,
Wen-mei W. Hwu,
Yale N. Patt:
On tuning the microarchitecture of an HPS implementation of the VAX.
MICRO 1987: 162-167 |
| 12 | EE | Stephen W. Melvin,
Yale N. Patt:
SPAM: a microcode based tool for tracing operating system events.
MICRO 1987: 168-171 |
| 11 | | Wen-mei W. Hwu,
Yale N. Patt:
Checkpoint Repair for High-Performance Out-of-Order Execution Machines.
IEEE Trans. Computers 36(12): 1496-1514 (1987) |
| 1986 |
|---|
| 10 | | Alvin M. Despain,
Yale N. Patt,
Tep P. Dobry,
Jung-Herng Chang,
Wayne Citrin:
High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation.
COMPCON 1986: 178-185 |
| 9 | | Yale N. Patt,
Wen-mei W. Hwu,
Stephen W. Melvin,
Michael Shebanow,
Chein Chen,
Jiajuin Wei:
Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers.
COMPCON 1986: 254-258 |
| 8 | | Wen-mei W. Hwu,
Yale N. Patt:
HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality.
ISCA 1986: 297-306 |
| 1985 |
|---|
| 7 | | Alvin M. Despain,
Yale N. Patt:
Aquarius - A High Performance Computing System for Symbolic/Numeric Applications.
COMPCON 1985: 376-382 |
| 6 | | Tep P. Dobry,
Alvin M. Despain,
Yale N. Patt:
Performance Studies of a Prolog Machine Architecture.
ISCA 1985: 180-190 |
| 5 | | David B. Aspinwall,
Yale N. Patt:
Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic - Implementation Issues, Measurements, and Analysis.
IEEE Trans. Computers 34(8): 692-708 (1985) |
| 1984 |
|---|
| 4 | | Alvin M. Despain,
Yale N. Patt:
The Aquarius Project.
COMPCON 1984: 364-368 |
| 1975 |
|---|
| 3 | | Serafino Amoroso,
Gerald Cooper,
Yale N. Patt:
Some Clarifications of the Concept of a Garden-of-Eden Configuration.
J. Comput. Syst. Sci. 10(1): 77-82 (1975) |
| 1972 |
|---|
| 2 | | Serafino Amoroso,
Yale N. Patt:
Decision Procedures for Surjectivity and Injectivity of Parallel Maps for Tessellation Structures.
J. Comput. Syst. Sci. 6(5): 448-464 (1972) |
| 1969 |
|---|
| 1 | EE | Yale N. Patt:
Variable length tree structures having minimum average search time.
Commun. ACM 12(2): 72-76 (1969) |
