Jude A. Rivers

2008
18	EE	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Online Estimation of Architectural Vulnerability Factor for Soft Errors. ISCA 2008: 341-352
17	EE	Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Metrics for Architecture-Level Lifetime Reliability Analysis. ISPASS 2008: 202-212
16	EE	Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves: Phaser: Phased methodology for modeling the system-level effects of soft errors. IBM Journal of Research and Development 52(3): 293-306 (2008)
2007
15	EE	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions. DSN 2007: 266-275
14	EE	Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose: A Framework for Architecture-Level Lifetime Reliability Modeling. DSN 2007: 534-543
2005
13	EE	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers: SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors. DSN 2005: 496-505
12	EE	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Exploiting Structural Duplication for Lifetime Reliability Enhancement. ISCA 2005: 520-531
11	EE	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Lifetime Reliability: Toward an Architectural Solution. IEEE Micro 25(3): 70-80 (2005)
2004
10	EE	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: The Impact of Technology Scaling on Lifetime Reliability. DSN 2004: 177-
9	EE	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: The Case for Lifetime Reliability-Aware Microprocessors. ISCA 2004: 276-287
2003
8	EE	Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno: Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325
1999
7	EE	Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999)
1998
6	EE	Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens: Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456
5	EE	Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson: mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS 1998: 19-26
1997
4		Jude A. Rivers, Edward S. Tam, Edward S. Davidson: On Effective Data Supply For Multi-Issue Processors. ICCD 1997: 519-528
3	EE	Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin: On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56
1996
2		Jude A. Rivers, Edward S. Davidson: Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. ICPP, Vol. 1 1996: 154-163
1		Jude A. Rivers, Edward S. Davidson: Performance Issues in Integrating Temporality-Based Caching with Prefetching. Perform. Eval. 27/28(4): 189-207 (1996)

Coauthor Index

1	Sarita V. Adve	[9] [10] [11] [12] [13] [15] [17] [18]
2	Luiz C. Alves	[16]
3	Sameh W. Asaad	[8]
4	Todd M. Austin	[3]
5	Pradip Bose	[9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
6	Ethan H. Cannon	[16]
7	Edward S. Davidson	[1] [2] [3] [4] [5] [6] [7]
8	Matthew K. Farrens	[6]
9	Zhigang Hu	[14]
10	Prabhakar Kudva	[16]
11	Xiaodong Li	[13] [15] [18]
12	Jaime H. Moreno	[8]
13	Pradeep Ramachandran	[17]
14	Pia N. Sanda	[16]
15	Jeonghee Shin	[14]
16	Jayanth Srinivasan	[9] [10] [11] [12]
17	Vijayalakshmi Srinivasan	[7]
18	Edward S. Tam	[4] [5] [6] [7]
19	Gary S. Tyson	[3] [5] [6] [7]
20	John-David Wellman	[8] [16]
21	Victor V. Zyuban	[14]