2008 |
70 | EE | Yukari Ishida,
Hirotaka Nosato,
Eiichi Takahashi,
Masahiro Murakawa,
Isamu Kajitani,
Tatsumi Furuya,
Tetsuya Higuchi:
Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation.
ICES 2008: 237-248 |
2007 |
69 | EE | Tetsuaki Matsunawa,
Hirokazu Nosato,
Hidenori Sakanashi,
Masahiro Murakawa,
Eiichi Takahashi,
Tsuneo Terasawa,
Toshihiko Tanaka,
Osamu Suga,
Tetsuya Higuchi:
Adaptive Optical Proximity Correction Using an Optimization Method.
CIT 2007: 853-860 |
68 | EE | Yosuke Iijima,
Masahiro Murakawa,
Yuji Kasai,
Eiichi Takahashi,
Tetsuya Higuchi:
Proposal of transmission line modeling using multi-objective optimization techniques.
IEEE Congress on Evolutionary Computation 2007: 2094-2100 |
2006 |
67 | | Adrian Stoica,
Tughrul Arslan,
Martin Suess,
Senay Yalçin,
Didier Keymeulen,
Tetsuya Higuchi,
Ricardo Salem Zebulum,
Nizamettin Aydin:
First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey
IEEE Computer Society 2006 |
66 | EE | Hirokazu Nosato,
Masahiro Murakawa,
Tetsuya Higuchi:
Automatic Alignment of Multiple Optical Components Using Genetic Algorithm.
AHS 2006: 67-73 |
65 | EE | Yuji Kasai,
Kiyoshi Miyashita,
Hidenori Sakanashi,
Eiichi Takahashi,
Masaya Iwata,
Masahiro Murakawa,
Kiyoshi Watanabe,
Yukihiro Ueda,
Kaoru Takasuka,
Tetsuya Higuchi:
An Image Rejection Mixer with AI-Based Improved Performance for WCDMA Applications.
IEICE Transactions 89-C(6): 717-724 (2006) |
2005 |
64 | EE | Masahiro Murakawa,
Mitiko Miura-Mattausch,
Tetsuya Higuchi:
Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm.
ASP-DAC 2005: 204-207 |
63 | EE | Yuji Kasai,
Eiichi Takahashi,
Masaya Iwata,
Yosuke Iijima,
Hidenori Sakanashi,
Masahiro Murakawa,
Tetsuya Higuchi:
Adaptive Waveform Control in a Data Transceiver for Multi-speed IEEE1394 and USB Communication.
ICES 2005: 198-204 |
2004 |
62 | EE | Masahiro Murakawa,
Eiichi Takahashi,
Tatsuya Susa,
Tetsuya Higuchi:
Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins.
SMC (4) 2004: 3670-3674 |
61 | EE | Hirokazu Nosato,
Taro Itatani,
Masahiro Murakawa,
Tetsuya Higuchi,
Hitoshi Noguchi:
Automatic wave-front correction of a femtosecond laser using genetic algorithm.
SMC (4) 2004: 3675-3679 |
60 | EE | Masahiro Murakawa,
Yoshihiro Noda,
Tetsuya Higuchi:
An automatic fiber alignment system using genetic algorithms.
Systems and Computers in Japan 35(11): 80-90 (2004) |
2003 |
59 | EE | Masahiro Murakawa,
Hirokazu Nosato,
Tetsuya Higuchi:
Automatic Optical Fiber Alignment System Using Genetic Algorithms.
Artificial Evolution 2003: 129-140 |
58 | EE | Eiichi Takahashi,
Masahiro Murakawa,
Yuji Kasai,
Tetsuya Higuchi:
Power Dissipation Reductions with Genetic Algorithms.
Evolvable Hardware 2003: 111-116 |
2001 |
57 | | Yong Liu,
Kiyoshi Tanaka,
Masaya Iwata,
Tetsuya Higuchi,
Moritoshi Yasunaga:
Evolvable Systems: From Biology to Hardware, 4th International Conference, ICES 2001 Tokyo, Japan, October 3-5, 2001, Proceedings
Springer 2001 |
56 | EE | Hidenori Sakanashi,
Masaya Iwata,
Tetsuya Higuchi:
A Lossless Compression Method for Halftone Images Using Evolvable Hardware.
ICES 2001: 314-326 |
55 | EE | Hirokazu Nosato,
Yuji Kasai,
Taro Itatani,
Masahiro Murakawa,
Tatsumi Furuya,
Tetsuya Higuchi:
Evolvable Optical Systems and Their Applications.
ICES 2001: 327-340 |
54 | EE | Masaya Iwata,
Isamu Kajitani,
Yong Liu,
Nobuki Kajihara,
Tetsuya Higuchi:
Implementation of a Gate-Level Evolvable Hardware Chip.
ICES 2001: 38-49 |
2000 |
53 | EE | Neil Marston,
Eiichi Takahashi,
Masahiro Murakawa,
Yuji Kasai,
Tetsuya Higuchi,
Toshio Adachi,
Kaoru Takasuka:
An Evolutionary Approach to GHz Digital Systems.
Evolvable Hardware 2000: 125-132 |
52 | | Yasuo Takehisa,
Hidenori Sakanashi,
Tetsuya Higuchi:
Adaptive Wavelet Transform for Lossless Compression using Genetic Algorithm.
GECCO 2000: 259-266 |
51 | EE | Yuji Kasai,
Hidenori Sakanashi,
Masahiro Murakawa,
Shogo Kiryu,
Neil Marston,
Tetsuya Higuchi:
Initial Evaluation of an Evolvable Microwave Circuit.
ICES 2000: 103-112 |
50 | | Yong Liu,
Masaya Iwata,
Tetsuya Higuchi,
Didier Keymeulen:
An Integrated On-Line Learning System for Evolving Programmable Logic Array Controllers.
PPSN 2000: 589-598 |
49 | | Yong Liu,
Xin Yao,
Tetsuya Higuchi:
Evolutionary ensembles with negative correlation learning.
IEEE Trans. Evolutionary Computation 4(4): 380-387 (2000) |
48 | EE | Masaya Iwata,
Isamu Kajitani,
Masahiro Murakawa,
Yuji Hirao,
Hitoshi Iba,
Tetsuya Higuchi:
Pattern recognition system using evolvable hardware.
Systems and Computers in Japan 31(4): 1-11 (2000) |
1999 |
47 | | Isamu Kajitani,
Tsutomu Hoshino,
Nobuki Kajihara,
Masaya Iwata,
Tetsuya Higuchi:
An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller.
AAAI/IAAI 1999: 182-187 |
46 | EE | Tetsuya Higuchi,
Nobuki Kajihara:
Evolvable Hardware Chips for Industrial Applications.
Commun. ACM 42(4): 60-66 (1999) |
45 | | Masahiro Murakawa,
Shuji Yoshizawa,
Isamu Kajitani,
Xin Yao,
Nobuki Kajihara,
Masaya Iwata,
Tetsuya Higuchi:
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing.
IEEE Trans. Computers 48(6): 628-639 (1999) |
44 | | Tetsuya Higuchi,
Masaya Iwata,
Didier Keymeulen,
Hidenori Sakanashi,
Masahiro Murakawa,
Isamu Kajitani,
Eiichi Takahashi,
Kenji Toda,
Mehrdad Salami,
Nobuki Kajihara,
Nobuyuki Otsu:
Real-world applications of analog and digital evolvable hardware .
IEEE Trans. Evolutionary Computation 3(3): 220-235 (1999) |
43 | | Xin Yao,
Tetsuya Higuchi:
Promises and challenges of evolvable hardware.
IEEE Transactions on Systems, Man, and Cybernetics, Part C 29(1): 87-97 (1999) |
1998 |
42 | | Hidenori Sakanashi,
Mehrdad Salami,
Masaya Iwata,
Shogo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression.
AAAI/IAAI 1998: 486-491 |
41 | EE | Mehrdad Salami,
Hidenori Sakanashi,
Masaharu Tanaka,
Masaya Iwata,
Takio Kurita,
Tetsuya Higuchi:
On-Line Compression of High Precision Printer Images by Evolvable Hardware.
Data Compression Conference 1998: 219-228 |
40 | | Didier Keymeulen,
Masaya Iwata,
Kenji Konaka,
Ryouhei Suzuki,
Yasuo Kuniyoshi,
Tetsuya Higuchi:
Off-Line Model-Free and On-Line Model-Based Evolution for Tracking Navigation Using Evolvable Hardware.
EvoRobots 1998: 211-226 |
39 | EE | Isamu Kajitani,
Tsutomu Hoshino,
Daisuke Nishikawa,
Hiroshi Yokoi,
Shougo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Masaya Iwata,
Didier Keymeulen,
Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.
ICES 1998: 1-12 |
38 | EE | Masaharu Tanaka,
Hidenori Sakanashi,
Mehrdad Salami,
Masaya Iwata,
Takio Kurita,
Tetsuya Higuchi:
Data Compression for Digital Color Electrophotographic Printer with Evolvable Hardware.
ICES 1998: 106-114 |
37 | EE | Masahiro Murakawa,
Shuji Yoshizawa,
Toshio Adachi,
Shiro Suzuki,
Kaoru Takasuka,
Masaya Iwata,
Tetsuya Higuchi:
Analogue EHW Chip for Intermediate Frequency Filters.
ICES 1998: 134-143 |
36 | | Masahiro Murakawa,
Kazuyuki Hiraoka,
Tetsuya Higuchi,
Tatsumi Furuya,
Shuji Yoshizawa:
Adaptive Blind Equalization Using Bottleneck Networks Implemented by Evolvable Hardware.
ICONIP 1998: 89-92 |
35 | | Didier Keymeulen,
Masaya Iwata,
Yasuo Kuniyoshi,
Tetsuya Higuchi:
Online Evolution for a Self-Adapting Robotic Navigation System Using Evolvable Hardware.
Artificial Life 4(4): 359-393 (1998) |
34 | | Didier Keymeulen,
Masaya Iwata,
Kenji Konaka,
Yasuo Kuniyoshi,
Tetsuya Higuchi:
Evolvable Hardware: A Robot Navigation System Testbed.
New Generation Comput. 16(2): 97-122 (1998) |
1997 |
33 | EE | Didier Keymeulen,
Kenji Konaka,
Masaya Iwata,
Yasuo Kuniyoshi,
Tetsuya Higuchi:
Robot Learning Using Gate-Level Evolvable Hardware.
EWLR 1997: 173- |
32 | | Masahiro Murakawa,
Shuji Yoshizawa,
Isamu Kajitani,
Tetsuya Higuchi:
On-line Adaptation of Neural Networks with Evolvable Hardware.
ICGA 1997: 792-800 |
31 | | Masahiro Murakawa,
Shuji Yoshizawa,
Isamu Kajitani,
Tetsuya Higuchi:
Evolvable Hardware for Generalized Neural Networks.
IJCAI 1997: 1146-1155 |
30 | | Ian Frank,
Bernard Manderick,
Tetsuya Higuchi:
Recent Advances in Evolvable Systems - ICES 96 (International Conference on Evolvable Systems).
Evolutionary Computation 5(1): 105-114 (1997) |
1996 |
29 | | Tetsuya Higuchi,
Masaya Iwata,
Weixin Liu:
Evolvable Systems: From Biology to Hardware, First International Conference, ICES 96, Tsukuba, Japan, October 7-8, 1996, Proceedings
Springer 1996 |
28 | | Mehrdad Salami,
Masahiro Murakawa,
Tetsuya Higuchi:
Data Compression Based on Evolvable Hardware.
ICES 1996: 169-179 |
27 | | Weixin Liu,
Masahiro Murakawa,
Tetsuya Higuchi:
ATM Cell Scheduling by Function Level Evolvable Hardware.
ICES 1996: 180-192 |
26 | | Didier Keymeulen,
Marc Durantez,
Kenji Konaka,
Yasuo Kuniyoshi,
Tetsuya Higuchi:
An Evolutionary Robot Navigation System Using a Gate-Level Evolvable Hardware.
ICES 1996: 195-209 |
25 | | Bernard Manderick,
Tetsuya Higuchi:
Evolvable Hardware: An Outlook.
ICES 1996: 305-311 |
24 | | Hitoshi Iba,
Masaya Iwata,
Tetsuya Higuchi:
Machine Learning Approach to Gate-Level Evolvable Hardware.
ICES 1996: 327-343 |
23 | | Masahiro Murakawa,
Shuji Yoshizawa,
Tetsuya Higuchi:
Adaptive Equalization of Digital Communication Channels Using Evolvable Hardware.
ICES 1996: 379-389 |
22 | | Hidenori Sakanashi,
Tetsuya Higuchi,
Hitoshi Iba,
Yukinori Kakazu:
Evolution of Binary Decision Diagrams for Digital Circuit Design Using Genetic Programming.
ICES 1996: 470-481 |
21 | | Xin Yao,
Tetsuya Higuchi:
Promises and Challenges of Evolvable Hardware.
ICES 1996: 55-78 |
20 | | Isamu Kajitani,
Tsutomu Hoshino,
Masaya Iwata,
Tetsuya Higuchi:
Variable Length Chromosome GA for Evolvable Hardware.
International Conference on Evolutionary Computation 1996: 443-447 |
19 | | Hidenori Sakanashi,
Tetsuya Higuchi,
Hitoshi Iba,
Yukinori Kakazu:
An Approach for Genetic Synthesizer of Binary Decision Diagram.
International Conference on Evolutionary Computation 1996: 559-564 |
18 | | Masahiro Murakawa,
Shuji Yoshizawa,
Isamu Kajitani,
Tatsumi Furuya,
Masaya Iwata,
Tetsuya Higuchi:
Hardware Evolution at Function Level.
PPSN 1996: 62-71 |
17 | | Masaya Iwata,
Isamu Kajitani,
Hitoshi Yamada,
Hitoshi Iba,
Tetsuya Higuchi:
A Pattern Recognition System Using Evolvable Hardware.
PPSN 1996: 761-770 |
1995 |
16 | | Tetsuya Higuchi,
Masaya Iwata,
Isamu Kajitani,
Hitoshi Iba,
Yuji Hirao,
Tatsumi Furuya,
Bernard Manderick:
Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems.
Towards Evolvable Hardware 1995: 118-135 |
1994 |
15 | EE | Kozo Oi,
Eiichiro Sumita,
Osamu Furuse,
Hitoshi Iida,
Tetsuya Higuchi:
Real-Time Spoken Language Translation Using Associative Processors.
ANLP 1994: 101-106 |
14 | | Tetsuya Higuchi,
Hitoshi Iba,
Bernard Manderick:
Applying Evolvable Hardware to Autonomous Agents.
PPSN 1994: 524-533 |
13 | | Tetsuya Higuchi,
Ken'ichi Handa,
Naoto Takahashi,
Tatsumi Furuya,
Hitoshi Iida,
Eiichiro Sumita,
Kozo Oi,
Hiroaki Kitano:
The IXM2 Parallel Associative Processor for AI.
IEEE Computer 27(11): 53-63 (1994) |
1993 |
12 | | Eiichiro Sumita,
Kozo Oi,
Osamu Furuse,
Hitoshi Iida,
Tetsuya Higuchi,
Naoto Takahashi,
Hiroaki Kitano:
Example-Based Machine Translation on Massively Parallel Processors.
IJCAI 1993: 1283-1289 |
11 | | Hitoshi Iba,
Tetsuya Higuchi,
Hugo de Garis,
Taisuke Sato:
Evolutionary Learning Strategy using Bug-Based Search.
IJCAI 1993: 960-966 |
1992 |
10 | | Hitoshi Iba,
Sumitaka Akiba,
Tetsuya Higuchi,
Taisuke Sato:
BUGS: A Bug-Based Search Strategy using Genetic Algorithms.
PPSN 1992: 167- |
1991 |
9 | | Hiroaki Kitano,
Tetsuya Higuchi:
High Performance Memory-Based Translation on IXM2 Massively Parallel Associative Memory Processor.
AAAI 1991: 149-154 |
8 | | Tetsuya Higuchi,
Hiroaki Kitano,
Tatsumi Furuya,
Ken'ichi Handa,
Akio Kokubu,
Naoto Takahashi:
IXM2: A Parallel Associative Processor for Knowledge Processing.
AAAI 1991: 296-303 |
7 | | Hiroaki Kitano,
Stephen F. Smith,
Tetsuya Higuchi:
GA-1: A Parallel Associative Memory Processor for Rule Learning with Genetic Algorithms.
ICGA 1991: 311-317 |
6 | | Hiroaki Kitano,
James A. Hendler,
Tetsuya Higuchi,
Dan I. Moldovan,
David L. Waltz:
Massively Parallel Artificial Intelligence.
IJCAI 1991: 557-562 |
5 | | Hiroaki Kitano,
Tetsuya Higuchi:
Massively Parallel Memory-Based Parsing.
IJCAI 1991: 918-924 |
4 | EE | Tetsuya Higuchi,
Tatsumi Furuya,
Ken'ichi Handa,
Naoto Takahashi,
Hiroyasu Nishiyama,
Akio Kokubu:
IXM2: A Parallel Associative Processor.
ISCA 1991: 22-31 |
1989 |
3 | | Tetsuya Higuchi,
Tatsumi Furuya,
Hiroyuki Kusumoto,
Ken'ichi Handa,
Akio Kokubu:
The Prototype of a Semantic Network Machine IXM.
ICPP (1) 1989: 217-224 |
1987 |
2 | | Tatsumi Furuya,
Tetsuya Higuchi,
Hiroyuki Kusumoto,
Ken'ichi Handa,
Akio Kokubu:
Architectural Evaluation of a Semantic Network Machine.
IWDM 1987: 544-556 |
1986 |
1 | | Tetsuya Higuchi,
Tatsumi Furuya,
Hiroyuki Kusumoto,
Ken'ichi Handa,
Akio Kokubu:
The IX Supercomputer for Knowledge-Based Systems.
FJCC 1986: 1041-1048 |