| 2009 |
|---|
| 200 | EE | Ferad Zyulkyarov,
Vladimir Gajinov,
Osman S. Unsal,
Adrián Cristal,
Eduard Ayguadé,
Tim Harris,
Mateo Valero:
Atomic quake: using transactional memory in an interactive multiplayer game server.
PPOPP 2009: 25-34 |
| 199 | EE | Chinmay Eishan Kulkarni,
Osman S. Unsal,
Adrián Cristal,
Eduard Ayguadé,
Mateo Valero:
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions.
PPOPP 2009: 307-308 |
| 198 | EE | Oliverio J. Santana,
Ayose Falcón,
Alex Ramírez,
Mateo Valero:
DIA: A Complexity-Effective Decoding Architecture.
IEEE Trans. Computers 58(4): 448-462 (2009) |
| 2008 |
|---|
| 197 | EE | Javier Verdú,
Mario Nemirovsky,
Mateo Valero:
MultiLayer processing - an execution model for parallel stateful packet processing.
ANCS 2008: 79-88 |
| 196 | EE | Carlos Boneti,
Francisco J. Cazorla,
Roberto Gioiosa,
Mateo Valero:
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation.
ARCS 2008: 173-187 |
| 195 | EE | Cristian Perfumo,
Nehir Sönmez,
Srdjan Stipic,
Osman S. Unsal,
Adrián Cristal,
Tim Harris,
Mateo Valero:
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment.
Conf. Computing Frontiers 2008: 67-78 |
| 194 | EE | Pedro A. Castillo,
Antonio Miguel Mora,
Juan Julián Merelo Guervós,
Juan Luís Jiménez Laredo,
Miquel Moretó,
Francisco J. Cazorla,
Mateo Valero,
Sally A. McKee:
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks.
EvoWorkshops 2008: 175-183 |
| 193 | EE | Tanausú Ramírez,
Alex Pajuelo,
Oliverio J. Santana,
Mateo Valero:
Runahead Threads to improve SMT performance.
HPCA 2008: 149-158 |
| 192 | EE | Alejandro García,
Oliverio J. Santana,
Enrique Fernández,
Pedro Medina,
Mateo Valero:
LPA: A First Approach to the Loop Processor Architecture.
HiPEAC 2008: 273-287 |
| 191 | EE | Mateo Valero,
Jesús Labarta:
Supercomputing for the Future, Supercomputing from the Past (Keynote).
HiPEAC 2008: 3-5 |
| 190 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
MLP-Aware Dynamic Cache Partitioning.
HiPEAC 2008: 337-352 |
| 189 | EE | Carmelo Acosta,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.
ICPP 2008: 173-181 |
| 188 | EE | Pedro A. Castillo Valdivieso,
Juan Julián Merelo Guervós,
Miquel Moretó,
Francisco J. Cazorla,
Mateo Valero,
Antonio Miguel Mora,
Juan Luís Jiménez Laredo,
Sally A. McKee:
Evolutionary system for prediction and optimization of hardware architecture performance.
IEEE Congress on Evolutionary Computation 2008: 1941-1948 |
| 187 | EE | Carlos Boneti,
Roberto Gioiosa,
Francisco J. Cazorla,
Julita Corbalán,
Jesús Labarta,
Mateo Valero:
Balancing HPC applications through smart allocation of resources in MT processors.
IPDPS 2008: 1-12 |
| 186 | EE | Miquel Pericàs,
Adrián Cristal,
Francisco J. Cazorla,
Ruden González,
Alexander V. Veidenbaum,
Daniel A. Jiménez,
Mateo Valero:
A Two-Level Load/Store Queue Based on Execution Locality.
ISCA 2008: 25-36 |
| 185 | EE | Carlos Boneti,
Francisco J. Cazorla,
Roberto Gioiosa,
Alper Buyuktosunoglu,
Chen-Yong Cher,
Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor.
ISCA 2008: 415-426 |
| 184 | EE | Isidro Gonzalez,
Marco Galluzzi,
Alexander V. Veidenbaum,
Marco A. Ramírez,
Adrián Cristal,
Mateo Valero:
A distributed processor state management architecture for large-window processors.
MICRO 2008: 11-22 |
| 183 | EE | Sebastian Isaza,
Friman Sánchez,
Georgi Gaydadjiev,
Alex Ramírez,
Mateo Valero:
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.
SAMOS 2008: 53-64 |
| 182 | EE | Carlos Boneti,
Roberto Gioiosa,
Francisco J. Cazorla,
Mateo Valero:
A dynamic scheduler for balancing HPC applications.
SC 2008: 41 |
| 181 | EE | Miquel Pericàs,
Ricardo Chaves,
Georgi Gaydadjiev,
Stamatis Vassiliadis,
Mateo Valero:
Vectorized AES Core for High-throughput Secure Environments.
VECPAR 2008: 83-94 |
| 180 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
Power-efficient VLIW design using clustering and widening.
IJES 3(3): 141-149 (2008) |
| 179 | EE | Milos Milovanovic,
Roger Ferrer,
Vladimir Gajinov,
Osman S. Unsal,
Adrián Cristal,
Eduard Ayguadé,
Mateo Valero:
Nebelung: Execution Environment for Transactional OpenMP.
International Journal of Parallel Programming 36(3): 326-346 (2008) |
| 2007 |
|---|
| 178 | EE | Marco Galluzzi,
Enrique Vallejo,
Adrián Cristal,
Fernando Vallejo,
Ramón Beivide,
Per Stenström,
James E. Smith,
Mateo Valero:
Implicit Transactional Memory in Kilo-Instruction Multiprocessors.
Asia-Pacific Computer Systems Architecture Conference 2007: 339-353 |
| 177 | EE | Sasa Tomic,
Adrián Cristal,
Osman S. Unsal,
Mateo Valero:
Hardware Transactional Memory with Operating System Support, HTMOS.
Euro-Par Workshops 2007: 8-17 |
| 176 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
Online Prediction of Applications Cache Utility.
ICSAMOS 2007: 169-177 |
| 175 | EE | Francisco J. Cazorla,
Enrique Fernández,
Peter M. W. Knijnenburg,
Alex Ramírez,
Rizos Sakellariou,
Mateo Valero:
On the Problem of Minimizing Workload Execution Time in SMT Processors.
ICSAMOS 2007: 66-73 |
| 174 | EE | Jesús Alastruey,
Teresa Monreal,
Víctor Viñals,
Mateo Valero:
Microarchitectural Support for Speculative Register Renaming.
IPDPS 2007: 1-10 |
| 173 | EE | Mauricio Alvarez,
Esther Salamí,
Alex Ramírez,
Mateo Valero:
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.
ISPASS 2007: 62-71 |
| 172 | EE | Milos Milovanovic,
Roger Ferrer,
Osman S. Unsal,
Adrián Cristal,
Xavier Martorell,
Eduard Ayguadé,
Jesús Labarta,
Mateo Valero:
Transactional Memory and OpenMP.
IWOMP 2007: 37-53 |
| 171 | EE | Miquel Pericàs,
Adrián Cristal,
Francisco J. Cazorla,
Ruben Gonzalez,
Daniel A. Jiménez,
Mateo Valero:
A Flexible Heterogeneous Multi-Core Architecture.
PACT 2007: 13-24 |
| 170 | EE | Javier Vera,
Francisco J. Cazorla,
Alex Pajuelo,
Oliverio J. Santana,
Enrique Fernández,
Mateo Valero:
FAME: FAirly MEasuring Multithreaded Architectures.
PACT 2007: 305-316 |
| 169 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
MLP-Aware Dynamic Cache Partitioning.
PACT 2007: 418 |
| 168 | EE | Tanausú Ramírez,
Alex Pajuelo,
Oliverio J. Santana,
Mateo Valero:
Runahead Threads: Reducing Resource Contention in SMT Processors.
PACT 2007: 423 |
| 167 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups.
Computer Architecture Letters 6(1): 1-4 (2007) |
| 166 | EE | Tim Harris,
Adrián Cristal,
Osman S. Unsal,
Eduard Ayguadé,
Fabrizio Gagliardi,
Burton Smith,
Mateo Valero:
Transactional Memory: An Overview.
IEEE Micro 27(3): 8-29 (2007) |
| 165 | EE | Oliverio J. Santana,
Alex Ramírez,
Mateo Valero:
Enlarging Instruction Streams.
IEEE Trans. Computers 56(10): 1342-1357 (2007) |
| 2006 |
|---|
| 164 | EE | Tanausú Ramírez,
Alex Pajuelo,
Oliverio J. Santana,
Mateo Valero:
Kilo-instruction processors, runahead and prefetching.
Conf. Computing Frontiers 2006: 269-278 |
| 163 | EE | Jesús Alastruey,
Teresa Monreal,
Víctor Viñals,
Mateo Valero:
Speculative early register release.
Conf. Computing Frontiers 2006: 291-302 |
| 162 | EE | Miquel Pericàs,
Adrián Cristal,
Ruben Gonzalez,
Daniel A. Jiménez,
Mateo Valero:
A decoupled KILO-instruction processor.
HPCA 2006: 53-64 |
| 161 | EE | Friman Sánchez,
Esther Salamí,
Alex Ramírez,
Mateo Valero:
Performance Analysis of Sequence Alignment Applications.
IISWC 2006: 51-60 |
| 160 | EE | Oliverio J. Santana,
Ayose Falcón,
Alex Ramírez,
Mateo Valero:
Branch predictor guided instruction decoding.
PACT 2006: 202-211 |
| 159 | EE | T. Y. Morad,
Uri C. Weiser,
A. Kolodnyt,
Mateo Valero,
Eduard Ayguadé:
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors.
Computer Architecture Letters 5(1): 14-17 (2006) |
| 158 | EE | Jorge García-Vidal,
Maribel March,
Llorenç Cerdà,
Jesús Corbal,
Mateo Valero:
A DRAM/SRAM Memory Scheme for Fast Packet Buffers.
IEEE Trans. Computers 55(5): 588-602 (2006) |
| 157 | EE | Francisco J. Cazorla,
Peter M. W. Knijnenburg,
Rizos Sakellariou,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Predictable Performance in SMT Processors: Synergy between the OS and SMTs.
IEEE Trans. Computers 55(7): 785-799 (2006) |
| 156 | EE | Javier Verdú,
Jorge García,
Mario Nemirovsky,
Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications.
J. Embedded Computing 2(1): 77-82 (2006) |
| 2005 |
|---|
| 155 | | Nader Bagherzadeh,
Mateo Valero,
Alex Ramírez:
Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005
ACM 2005 |
| 154 | | Thomas M. Conte,
Nacho Navarro,
Wen-mei W. Hwu,
Mateo Valero,
Theo Ungerer:
High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings
Springer 2005 |
| 153 | EE | Javier Verdú,
Jorge García,
Mario Nemirovsky,
Mateo Valero:
Architectural impact of stateful networking applications.
ANCS 2005: 11-18 |
| 152 | EE | Francisco J. Cazorla,
Peter M. W. Knijnenburg,
Rizos Sakellariou,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Architectural support for real-time task scheduling in SMT processors.
CASES 2005: 166-176 |
| 151 | EE | Marco A. Ramírez,
Adrián Cristal,
Mateo Valero,
Alexander V. Veidenbaum,
Luis Villa:
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.
ICCD 2005: 647-653 |
| 150 | EE | Carmelo Acosta,
Ayose Falcón,
Alex Ramírez,
Mateo Valero:
A Complexity-Effective Simultaneous Multithreading Architecture.
ICPP 2005: 157-164 |
| 149 | EE | Esther Salamí,
Mateo Valero:
A Vector-µSIMD-VLIW Architecture for Multimedia Applications.
ICPP 2005: 69-77 |
| 148 | EE | Rubén González,
Adrián Cristal,
Miquel Pericàs,
Mateo Valero,
Alexander V. Veidenbaum:
An asymmetric clustered processor based on value content.
ICS 2005: 61-70 |
| 147 | EE | Alex Pajuelo,
Antonio González,
Mateo Valero:
Control-Flow Independence Reuse via Dynamic Vectorization.
IPDPS 2005 |
| 146 | EE | Ayose Falcón,
Alex Ramírez,
Mateo Valero:
Effective Instruction Prefetching via Fetch Prestaging.
IPDPS 2005 |
| 145 | EE | Friman Sánchez,
Mauricio Alvarez,
Esther Salamí,
Alex Ramírez,
Mateo Valero:
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications.
ISPASS 2005: 167-176 |
| 144 | EE | Raimir Holanda,
Javier Verdú,
Jorge García,
Mateo Valero:
Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering.
ISPASS 2005: 219-225 |
| 143 | EE | Ayose Falcón,
Jared Stark,
Alex Ramírez,
Konrad K. Lai,
Mateo Valero:
Better Branch Prediction Through Prophet/Critic Hybrids.
IEEE Micro 25(1): 80-89 (2005) |
| 142 | EE | Adrián Cristal,
Oliverio J. Santana,
Francisco J. Cazorla,
Marco Galluzzi,
Tanausú Ramírez,
Miquel Pericàs,
Mateo Valero:
Kilo-Instruction Processors: Overcoming the Memory Wall.
IEEE Micro 25(3): 48-57 (2005) |
| 141 | EE | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Mateo Valero:
Software Trace Cache.
IEEE Trans. Computers 54(1): 22-35 (2005) |
| 140 | EE | Carlos Álvarez,
Jesús Corbal,
Mateo Valero:
Fuzzy Memoization for Floating-Point Multimedia Applications.
IEEE Trans. Computers 54(7): 922-927 (2005) |
| 139 | EE | Teresa Monreal,
Víctor Viñals,
Antonio González,
Mateo Valero:
Hardware support for early register release.
IJHPCN 3(2/3): 83-94 (2005) |
| 138 | EE | Alex Pajuelo,
Antonio González,
Mateo Valero:
Speculative execution for hiding memory latency.
SIGARCH Computer Architecture News 33(3): 49-56 (2005) |
| 137 | EE | Javier Verdú,
Jorge García,
Mario Nemirovsky,
Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications.
SIGARCH Computer Architecture News 33(3): 57-62 (2005) |
| 136 | EE | Esther Salamí,
Mateo Valero:
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications.
TACO 2(2): 199-219 (2005) |
| 2004 |
|---|
| 135 | EE | Marco Galluzzi,
Valentin Puente,
Adrián Cristal,
Ramón Beivide,
José-Ángel Gregorio,
Mateo Valero:
A first glance at Kilo-instruction based multiprocessors.
Conf. Computing Frontiers 2004: 212-221 |
| 134 | EE | Francisco J. Cazorla,
Peter M. W. Knijnenburg,
Rizos Sakellariou,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Predictable performance in SMT processors.
Conf. Computing Frontiers 2004: 433-443 |
| 133 | EE | Francisco J. Cazorla,
Peter M. W. Knijnenburg,
Rizos Sakellariou,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Implicit vs. Explicit Resource Allocation in SMT Processors.
DSD 2004: 44-51 |
| 132 | EE | Francisco J. Cazorla,
Peter M. W. Knijnenburg,
Rizos Sakellariou,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Feasibility of QoS for SMT.
Euro-Par 2004: 535-540 |
| 131 | EE | Adrián Cristal,
Oliverio J. Santana,
Mateo Valero:
Maintaining Thousands of In-flight Instructions.
Euro-Par 2004: 9-20 |
| 130 | EE | Ayose Falcón,
Alex Ramírez,
Mateo Valero:
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors.
HPCA 2004: 244-253 |
| 129 | EE | Adrián Cristal,
Daniel Ortega,
Josep Llosa,
Mateo Valero:
Out-of-Order Commit Processors.
HPCA 2004: 48-59 |
| 128 | EE | Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero,
Enrique Fernández:
DCache Warn: An I-Fetch Policy to Increase SMT Efficiency.
IPDPS 2004 |
| 127 | EE | Ayose Falcón,
Jared Stark,
Alex Ramírez,
Konrad Lai,
Mateo Valero:
Prophet/Critic Hybrid Branch Prediction.
ISCA 2004: 250-263 |
| 126 | EE | Rubén González,
Adrián Cristal,
Daniel Ortega,
Alexander V. Veidenbaum,
Mateo Valero:
A Content Aware Integer Register File Organization.
ISCA 2004: 314-324 |
| 125 | EE | Oliverio J. Santana,
Alex Ramírez,
Mateo Valero:
Reducing Fetch Architecture Complexity Using Procedure Inlining.
Interaction between Compilers and Computer Architectures 2004: 97-106 |
| 124 | EE | Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero,
Enrique Fernández:
Dynamically Controlled Resource Allocation in SMT Processors.
MICRO 2004: 171-182 |
| 123 | EE | Miquel Pericàs,
Rubén González,
Adrián Cristal,
Alexander V. Veidenbaum,
Mateo Valero:
An Optimized Front-End Physical Register File with Banking and Writeback Filtering.
PACS 2004: 1-14 |
| 122 | EE | Esther Salamí,
Mateo Valero:
Initial Evaluation of Multimedia Extensions on VLIW Architectures.
SAMOS 2004: 403-412 |
| 121 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
with Wide Functional Units.
SAMOS 2004: 88-97 |
| 120 | EE | Marco Galluzzi,
Ramón Beivide,
Valentin Puente,
José-Ángel Gregorio,
Adrián Cristal,
Mateo Valero:
Evaluating kilo-instruction multiprocessors.
WMPI 2004: 72-79 |
| 119 | EE | Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero,
Peter M. W. Knijnenburg,
Rizos Sakellariou,
Enrique Fernández:
QoS for High-Performance SMT Processors in Embedded Systems.
IEEE Micro 24(4): 24-31 (2004) |
| 118 | EE | Teresa Monreal,
Víctor Viñals,
José González,
Antonio González,
Mateo Valero:
Late Allocation and Early Release of Physical Registers.
IEEE Trans. Computers 53(10): 1244-1259 (2004) |
| 117 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Register Constrained Modulo Scheduling.
IEEE Trans. Parallel Distrib. Syst. 15(5): 417-430 (2004) |
| 116 | EE | Marco A. Ramírez,
Adrián Cristal,
Mateo Valero,
Alexander V. Veidenbaum,
Luis Villa:
A partitioned instruction queue to reduce instruction wakeup energy.
IJHPCN 1(4): 153-161 (2004) |
| 115 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
High-performance and low-power VLIW cores for numerical computations.
IJHPCN 1(4): 171-179 (2004) |
| 114 | EE | Adrián Cristal,
Josep Llosa,
Mateo Valero,
Daniel Ortega:
Future ILP processors.
IJHPCN 2(1): 1-10 (2004) |
| 113 | EE | Ayose Falcón,
Oliverio J. Santana,
Alex Ramírez,
Mateo Valero:
A latency-conscious SMT branch prediction architecture.
IJHPCN 2(1): 11-21 (2004) |
| 112 | EE | Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero,
Enrique Fernández:
Optimising long-latency-load-aware fetch policies for SMT processors.
IJHPCN 2(1): 45-54 (2004) |
| 111 | EE | Daniel Ortega,
Mateo Valero,
Eduard Ayguadé:
Dynamic Memory Instruction Bypassing.
International Journal of Parallel Programming 32(3): 199-224 (2004) |
| 110 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.
International Journal of Parallel Programming 32(6): 447-474 (2004) |
| 109 | EE | Adrián Cristal,
José F. Martínez,
Josep Llosa,
Mateo Valero:
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.
SIGARCH Computer Architecture News 32(3): 3-10 (2004) |
| 108 | EE | Oliverio J. Santana,
Alex Ramírez,
Josep-Lluis Larriba-Pey,
Mateo Valero:
A low-complexity fetch architecture for high-performance superscalar processors.
TACO 1(2): 220-245 (2004) |
| 107 | EE | Adrián Cristal,
Oliverio J. Santana,
Mateo Valero,
José F. Martínez:
Toward kilo-instruction processors.
TACO 1(4): 389-417 (2004) |
| 2003 |
|---|
| 106 | EE | Daniel Ortega,
Eduard Ayguadé,
Mateo Valero:
Dynamic memory instruction bypassing.
ICS 2003: 316-325 |
| 105 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Hierarchical Clustered Register File Organization for VLIW Processors.
IPDPS 2003: 77 |
| 104 | EE | Adrián Cristal,
Daniel Ortega,
Josep Llosa,
Mateo Valero:
Kilo-instruction Processors.
ISHPC 2003: 10-25 |
| 103 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.
ISHPC 2003: 113-126 |
| 102 | EE | Francisco J. Cazorla,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Improving Memory Latency Aware Fetch Policies for SMT Processors.
ISHPC 2003: 70-85 |
| 101 | EE | Ayose Falcón,
Oliverio J. Santana,
Alex Ramírez,
Mateo Valero:
Tolerating Branch Predictor Latency on SMT.
ISHPC 2003: 86-98 |
| 100 | EE | Marco A. Ramírez,
Adrián Cristal,
Alexander V. Veidenbaum,
Luis Villa,
Mateo Valero:
A Simple Low-Energy Instruction Wakeup Mechanism.
ISHPC 2003: 99-112 |
| 99 | EE | Sally A. McKee,
Zhen Fang,
Mateo Valero:
An MPEG-4 performance study for non-SIMD, general purpose architectures.
ISPASS 2003: 49-57 |
| 98 | EE | Jorge García,
Jesús Corbal,
Llorenç Cerdà,
Mateo Valero:
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers.
MICRO 2003: 373-386 |
| 97 | EE | Adrián Cristal,
José F. Martínez,
Josep Llosa,
Mateo Valero:
A Case for Resource-conscious Out-of-order Processors.
Computer Architecture Letters 2: (2003) |
| 96 | EE | Francisca Quintana,
Jesús Corbal,
Roger Espasa,
Mateo Valero:
A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications.
Theory Comput. Syst. 36(5): 575-593 (2003) |
| 2002 |
|---|
| 95 | EE | Esther Salamí,
Jesús Corbal,
Carlos Álvarez,
Mateo Valero:
Cost effective memory disambiguation for multimedia codes.
CASES 2002: 117-126 |
| 94 | EE | Hans Vandierendonck,
Alex Ramírez,
Koenraad De Bosschere,
Mateo Valero:
A Comparative Study of Redundancy in Trace Caches (Research Note).
Euro-Par 2002: 512-516 |
| 93 | EE | Teresa Monreal,
Víctor Viñals,
Antonio González,
Mateo Valero:
Hardware Schemes for Early Register Release.
ICPP 2002: 5-13 |
| 92 | EE | Daniel Ortega,
Eduard Ayguadé,
Jean-Loup Baer,
Mateo Valero:
Cost-Effective Compiler Directed Memory Prefetching and Bypassing.
IEEE PACT 2002: 189-198 |
| 91 | EE | Alex Pajuelo,
Antonio González,
Mateo Valero:
Speculative Dynamic Vectorization.
ISCA 2002: 271-280 |
| 90 | EE | Oliverio J. Santana,
Ayose Falcón,
Enrique Fernández,
Pedro Medina,
Alex Ramírez,
Mateo Valero:
A Comprehensive Analysis of Indirect Branch Prediction.
ISHPC 2002: 133-145 |
| 89 | EE | Ayose Falcón,
Oliverio J. Santana,
Pedro Medina,
Enrique Fernández,
Alex Ramírez,
Mateo Valero:
Studying New Ways for Improving Adaptive History Length Branch Predictors.
ISHPC 2002: 271-280 |
| 88 | EE | Jesús Corbal,
Roger Espasa,
Mateo Valero:
Three-dimensional memory vectorization for high bandwidth media memory systems.
MICRO 2002: 149-160 |
| 87 | EE | Alex Ramírez,
Oliverio J. Santana,
Josep-Lluis Larriba-Pey,
Mateo Valero:
Fetching instruction streams.
MICRO 2002: 371-382 |
| 86 | EE | Carlos Álvarez,
Jesús Corbal,
Esther Salamí,
Mateo Valero:
Initial Results on Fuzzy Floating Point Computation for Multimedia Processors.
Computer Architecture Letters 1: (2002) |
| 85 | | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Carlos Navarro,
Mateo Valero,
Josep Torrellas:
Software Trace Cache for Commercial Applications.
International Journal of Parallel Programming 30(5): 373-395 (2002) |
| 84 | EE | Rajagopalan Desikan,
Doug Burger,
Stephen W. Keckler,
Llorenc Cruz,
Fernando Latorre,
Antonio González,
Mateo Valero:
Errata on "Measuring Experimental Error in Microprocessor Simulation".
SIGARCH Computer Architecture News 30(1): 2-4 (2002) |
| 2001 |
|---|
| 83 | | Lionel M. Ni,
Mateo Valero:
Proceedings of the 2001 International Conference on Parallel Processing, ICPP 2002, 3-7 September 2001, Valencia, Spain
IEEE Computer Society 2001 |
| 82 | EE | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Mateo Valero:
Branch Prediction Using Profile Data.
Euro-Par 2001: 386-393 |
| 81 | EE | Stamatis Vassiliadis,
Francky Catthoor,
Mateo Valero,
Sorin Cotofana:
Topic 15+20: Multimedia and Embedded Systems.
Euro-Par 2001: 651-652 |
| 80 | EE | Jesús Corbal,
Roger Espasa,
Mateo Valero:
DLP + TLP Processors for the Next Generation of Media Workloads.
HPCA 2001: 219-228 |
| 79 | EE | Carlos Álvarez,
Jesús Corbal,
Esther Salamí,
Mateo Valero:
On the potential of tolerant region reuse for multimedia applications.
ICS 2001: 218-228 |
| 78 | EE | Daniel Ortega,
Mateo Valero,
Eduard Ayguadé:
A novel renaming mechanism that boosts software prefetching.
ICS 2001: 501-510 |
| 77 | EE | Jesús Corbal,
Roger Espasa,
Mateo Valero:
On the Efficiency of Reductions in µ-SIMD Media Extensions.
IEEE PACT 2001: 83- |
| 76 | EE | Alex Ramírez,
Luiz André Barroso,
Kourosh Gharachorloo,
Robert S. Cohn,
Josep-Lluis Larriba-Pey,
P. Geoffrey Lowney,
Mateo Valero:
Code layout optimizations for transaction processing workloads.
ISCA 2001: 155-164 |
| 75 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
MIRS: Modulo Scheduling with Integrated Register Spilling.
LCPC 2001: 239-253 |
| 74 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Modulo scheduling with integrated register spilling for clustered VLIW architectures.
MICRO 2001: 160-169 |
| 73 | EE | Francisca Quintana,
Jesús Corbal,
Roger Espasa,
Mateo Valero:
A cost effective architecture for vectorizable numerical and multimedia applications.
SPAA 2001: 103-112 |
| 72 | EE | Sriram Vajapeyam,
Mateo Valero:
Early 21st Century Processors - Guest Editors' Introduction.
IEEE Computer 34(4): 47-50 (2001) |
| 71 | EE | David López,
Josep Llosa,
Mateo Valero,
Eduard Ayguadé:
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.
IEEE Trans. Computers 50(10): 1033-1051 (2001) |
| 70 | EE | Josep Llosa,
Eduard Ayguadé,
Antonio González,
Mateo Valero,
Jason Eckhardt:
Lifetime-Sensitive Modulo Scheduling in a Production Environment.
IEEE Trans. Computers 50(3): 234-249 (2001) |
| 2000 |
|---|
| 69 | | Mateo Valero,
Kazuki Joe,
Masaru Kitsuregawa,
Hidehiko Tanaka:
High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings
Springer 2000 |
| 68 | | Mateo Valero,
Viktor K. Prasanna,
Sriram Vajapeyam:
High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings
Springer 2000 |
| 67 | EE | Silvia M. Müller,
Per Stenström,
Mateo Valero,
Stamatis Vassiliadis:
Parallel Computer Architecture.
Euro-Par 2000: 537-538 |
| 66 | EE | Carlos Navarro,
Alex Ramírez,
Josep-Lluis Larriba-Pey,
Mateo Valero:
On the Performance of Fetch Engines Running DSS Workloads.
Euro-Par 2000: 940-949 |
| 65 | EE | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Mateo Valero:
Trace Cache Redundancy: Red & Blue Traces.
HPCA 2000: 325- |
| 64 | EE | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Mateo Valero:
The Effect of Code Reordering on Branch Prediction.
IEEE PACT 2000: 189-198 |
| 63 | EE | José-Lorenzo Cruz,
Antonio González,
Mateo Valero,
Nigel P. Topham:
Multiple-banked register file architectures.
ISCA 2000: 316-325 |
| 62 | EE | Mateo Valero:
Architectures for One Billion of Transistors.
ISSS 2000: 62 |
| 61 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Two-level hierarchical register file organization for VLIW processors.
MICRO 2000: 137-146 |
| 60 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Improved spill code generation for software pipelined loops.
PLDI 2000: 134-144 |
| 59 | EE | Teresa Monreal,
Antonio González,
Mateo Valero,
José González,
Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers.
J. Instruction-Level Parallelism 2: (2000) |
| 1999 |
|---|
| 58 | EE | Pascal Sainrat,
Mateo Valero:
Instruction-Level Parallelism and Uniprocessor Architecture - Introduction.
Euro-Par 1999: 1241-1242 |
| 57 | EE | David López,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures.
ICPP 1999: 22-29 |
| 56 | EE | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Carlos Navarro,
Xavi Serrano,
Mateo Valero,
Josep Torrellas:
Optimization of Instruction Fetch for Decision Support Workloads.
ICPP 1999: 238-245 |
| 55 | EE | Daniel Ortega,
Ivan Martel,
Venkata Krishnan,
Eduard Ayguadé,
Mateo Valero:
Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures.
IEEE PACT 1999: 117-124 |
| 54 | EE | Francisca Quintana,
Jesús Corbal,
Roger Espasa,
Mateo Valero:
Adding a vector unit to a superscalar processor.
International Conference on Supercomputing 1999: 1-10 |
| 53 | EE | Alex Ramírez,
Josep-Lluis Larriba-Pey,
Carlos Navarro,
Josep Torrellas,
Mateo Valero:
Software trace cache.
International Conference on Supercomputing 1999: 119-126 |
| 52 | EE | Ivan Martel,
Daniel Ortega,
Eduard Ayguadé,
Mateo Valero:
Increasing effective IPC by exploiting distant parallelism.
International Conference on Supercomputing 1999: 348-355 |
| 51 | EE | Teresa Monreal,
Antonio González,
Mateo Valero,
José González,
Víctor Viñals:
Delaying Physical Register Allocation through Virtual-Physical Registers.
MICRO 1999: 186- |
| 50 | EE | Jesús Corbal,
Roger Espasa,
Mateo Valero:
Exploiting a New Level of DLP in Multimedia Applications.
MICRO 1999: 72- |
| 49 | | Veljko M. Milutinovic,
Mateo Valero:
Enhancing and Exploiting the Locality.
IEEE Trans. Computers 48(2): 97-99 (1999) |
| 48 | EE | Roger Espasa,
Mateo Valero:
A Simulation Study of Decoupled Vector Architectures.
The Journal of Supercomputing 14(2): 124-152 (1999) |
| 1998 |
|---|
| 47 | EE | Antonio González,
José González,
Mateo Valero:
Virtual-Physical Registers.
HPCA 1998: 175-184 |
| 46 | EE | Jesús Corbal,
Roger Espasa,
Mateo Valero:
Command Vector Memory Systems: High Performance at Low Cost.
IEEE PACT 1998: 68- |
| 45 | EE | Luis Villa,
Roger Espasa,
Mateo Valero:
A Performance Study of Out-of-order Vector Architectures and Short Registers.
International Conference on Supercomputing 1998: 37-44 |
| 44 | EE | Roger Espasa,
Mateo Valero,
James E. Smith:
Vector Architectures: Past, Present and Future.
International Conference on Supercomputing 1998: 425-432 |
| 43 | EE | David López,
Josep Llosa,
Mateo Valero,
Eduard Ayguadé:
Resource Widening Versus Replication: Limits and Performance-cost Trade-off.
International Conference on Supercomputing 1998: 441-448 |
| 42 | EE | David López,
Josep Llosa,
Mateo Valero,
Eduard Ayguadé:
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures.
MICRO 1998: 237-246 |
| 41 | | Luis Villa,
Roger Espasa,
Mateo Valero:
Registers Size Influence on Vector Architectures.
VECPAR 1998: 439-451 |
| 40 | | Francisca Quintana,
Roger Espasa,
Mateo Valero:
An ISA Comparison Between Superscalar and Vector Processors.
VECPAR 1998: 548-560 |
| 39 | | Josep Llosa,
Mateo Valero,
Eduard Ayguadé,
Antonio González:
Modulo Scheduling with Reduced Register Pressure.
IEEE Trans. Computers 47(6): 625-638 (1998) |
| 38 | | Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Quantitative Evaluation of Register Pressure on Software Pipelined Loops.
International Journal of Parallel Programming 26(2): 121-142 (1998) |
| 1997 |
|---|
| 37 | EE | Roger Espasa,
Mateo Valero:
Multithreaded Vector Architectures.
HPCA 1997: 237- |
| 36 | EE | Luis Villa,
Roger Espasa,
Mateo Valero:
Effective Usage of Vector Registers in Advanced Vector Architectures.
IEEE PACT 1997: 250-260 |
| 35 | EE | F. Jesús Sánchez,
Antonio González,
Mateo Valero:
Static Locality Analysis for Cache Management.
IEEE PACT 1997: 261-271 |
| 34 | EE | David López,
Mateo Valero,
Josep Llosa,
Eduard Ayguadé:
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs.
International Conference on Supercomputing 1997: 12-19 |
| 33 | EE | Roger Espasa,
Mateo Valero:
A Victim Cache for Vector Registers.
International Conference on Supercomputing 1997: 293-300 |
| 32 | EE | Antonio González,
Mateo Valero,
Nigel P. Topham,
Joan-Manuel Parcerisa:
Eliminating Cache Conflict Misses through XOR-Based Placement Functions.
International Conference on Supercomputing 1997: 76-83 |
| 31 | EE | Roger Espasa,
Mateo Valero,
James E. Smith:
Out-of-Order Vector Architectures.
MICRO 1997: 160-170 |
| 1996 |
|---|
| 30 | EE | Roger Espasa,
Mateo Valero:
Decoupled Vector Architectures.
HPCA 1996: 281-290 |
| 29 | EE | Josep Llosa,
Mateo Valero,
Eduard Ayguadé:
Heuristics for Register-Constrained Software Pipelining.
MICRO 1996: 250-261 |
| 28 | EE | Jordi Torres,
Eduard Ayguadé,
Jesús Labarta,
Mateo Valero:
Loop Parallelization: Revisiting Framework of Unimodular Transformations.
PDP 1996: 420-428 |
| 1995 |
|---|
| 27 | | Josep Llosa,
Mateo Valero,
Eduard Ayguadé:
Non-Consistent Dual Register Files to Reduce Register Pressure.
HPCA 1995: 22-31 |
| 26 | EE | Montse Peiron,
Mateo Valero,
Eduard Ayguadé,
Tomás Lang:
Vector Multiprocessors with Arbitrated Memory Access.
ISCA 1995: 243-252 |
| 25 | EE | Antonio González,
Carlos Aliagas,
Mateo Valero:
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality.
International Conference on Supercomputing 1995: 338-347 |
| 24 | EE | Josep Llosa,
Mateo Valero,
Eduard Ayguadé,
Antonio González:
Hypernode reduction modulo scheduling.
MICRO 1995: 350-360 |
| 23 | EE | Roger Espasa,
Mateo Valero,
David A. Padua,
Marta Jiménez,
Eduard Ayguadé:
Quantitative analysis of vector code.
PDP 1995: 452-463 |
| 22 | | Mateo Valero,
Tomás Lang,
Montse Peiron,
Eduard Ayguadé:
Conflict-Free Access for Streams in Multimodule Memories.
IEEE Trans. Computers 44(5): 634-646 (1995) |
| 1994 |
|---|
| 21 | | Mateo Valero,
Montse Peiron,
Eduard Ayguadé:
Memory Access Synchronization in Vector Multiprocessors.
CONPAR 1994: 414-425 |
| 20 | | Josep Llosa,
Mateo Valero,
José A. B. Fortes,
Eduard Ayguadé:
Using Sacks to Organize Registers in VLIW Machines.
CONPAR 1994: 628-639 |
| 19 | EE | Montse Peiron,
Mateo Valero,
Eduard Ayguadé:
Synchronized access to streams in SIMD vector multiprocessors.
International Conference on Supercomputing 1994: 23-32 |
| 18 | | Eduard Ayguadé,
Jordi Garcia,
Mercè Gironés,
Jesús Labarta,
Jordi Torres,
Mateo Valero:
Detecting and Using Affinity in an Automatic Data Distribution Tool.
LCPC 1994: 61-75 |
| 17 | | Mateo Valero,
Eduard Ayguadé,
Montse Peiron:
Network Synchronization and Out-of-Order Access to Vectors.
Parallel Processing Letters 4: 405-415 (1994) |
| 1993 |
|---|
| 16 | | Jordi Torres,
Eduard Ayguadé,
Jesús Labarta,
Mateo Valero:
Align and Distribute-based Linear Loop Transformations.
LCPC 1993: 321-339 |
| 1992 |
|---|
| 15 | EE | Mateo Valero,
Tomás Lang,
Eduard Ayguadé:
Conflict-free access of vectors with power-of-two strides.
ICS 1992: 149-156 |
| 14 | | Mateo Valero,
Tomás Lang,
José M. Llabería,
Montse Peiron,
Eduard Ayguadé,
Juan J. Navarro:
Increasing the Number of Strides for Conflict-Free Vector Access.
ISCA 1992: 372-381 |
| 13 | EE | Miguel Valero-García,
Juan J. Navarro,
José María Llabería,
Mateo Valero,
Tomás Lang:
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units.
VLSI Signal Processing 4(1): 7-25 (1992) |
| 1991 |
|---|
| 12 | | Miguel Valero-García,
Juan J. Navarro,
José J. M. Liabería,
Mateo Valero,
Tomás Lang:
Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units.
Algorithms and Parallel VLSI Architectures 1991: 25-38 |
| 11 | | Jordi Torres,
Eduard Ayguadé,
Jesús Labarta,
José M. Llabería,
Mateo Valero:
On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors.
EDMCC 1991: 173-182 |
| 10 | | Jesús Labarta,
Eduard Ayguadé,
Jordi Torres,
Mateo Valero,
José M. Llabería:
Balanced Loop Partitioning Using GTS.
LCPC 1991: 298-312 |
| 9 | | Mateo Valero,
Tomás Lang,
José María Llabería,
Montse Peiron,
Juan J. Navarro,
Eduard Ayguadé:
Conflict-Free Strides for Vectors in Matched Memories.
Parallel Processing Letters 1: 95-102 (1991) |
| 1989 |
|---|
| 8 | EE | Miguel Valero-García,
Juan J. Navarro,
José M. Llabería,
Mateo Valero:
Systematic Hardware Adaptation of Systolic Algorithms.
ISCA 1989: 96-104 |
| 7 | EE | Fernando J. Nuñez,
Mateo Valero:
A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem.
VLSI Signal Processing 1(2): 153-162 (1989) |
| 1987 |
|---|
| 6 | | Miguel Angel Fiol,
J. Luis A. Yebra,
Ignacio Alegre,
Mateo Valero:
A Discrete Optimization Problem in Local Networks and Data Alignment.
IEEE Trans. Computers 36(6): 702-713 (1987) |
| 1986 |
|---|
| 5 | | Juan J. Navarro,
José M. Llabería,
Mateo Valero:
Solving Matrix Problems with No Size Restriction on a Systolic Array Processor.
ICPP 1986: 676-683 |
| 4 | | Juan J. Navarro,
José M. Llabería,
Mateo Valero:
Computing Size-Independent Matrix Problems on Systolic Array Processors.
ISCA 1986: 271-278 |
| 1985 |
|---|
| 3 | | José M. Llabería,
Mateo Valero,
Enrique Herrada Lillo,
Jesús Labarta:
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering.
ISCA 1985: 414-421 |
| 1983 |
|---|
| 2 | | Tomás Lang,
Mateo Valero,
Miguel Angel Fiol:
Reduction of Connections for Multibus Organization.
IEEE Trans. Computers 32(8): 707-716 (1983) |
| 1982 |
|---|
| 1 | | Tomás Lang,
Mateo Valero,
Ignacio Alegre:
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors.
IEEE Trans. Computers 31(12): 1227-1234 (1982) |
