| |
| 2005 | ||
|---|---|---|
| 3 | EE | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137 |
| 2004 | ||
| 2 | EE | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273 |
| 1 | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948 | |
| 1 | Yao-Wen Chang | [1] [2] [3] |
| 2 | Jing-Yang Jou | [1] [2] [3] |