| |
| 2008 | ||
|---|---|---|
| 2 | EE | Theodore W. Manikas, Dale Teeters: Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells. ISMVL 2008: 197-201 |
| 2002 | ||
| 1 | Theodore W. Manikas, Gerald R. Kane: Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement. IWLS 2002: 27-30 | |
| 1 | Gerald R. Kane | [1] |
| 2 | Dale Teeters | [2] |