DSD 2005:
Porto,
Portugal
Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal.
IEEE Computer Society 2005, ISBN 0-7695-2433-8 BibTeX
Cover
Introduction
Keynote Speeches
SS2:
Dependability and Testing of Digital Systems,
Part 1. (S1)
System Synthesis,
Part 1. Power and Component Driven System Synthesis (S2)
Circuits Synthesis,
Part 1. Arithmetic (S3)
SS2:
Dependability and Testing of Digital Systems,
Part 2. (S4)
- Peter Filter, Hana Kubatova:
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST.
56-63
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- Lucía Costas, Juan J. Rodríguez-Andina:
Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection.
64-71
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- Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar:
Improved Fault Emulation for Synchronous Sequential Circuits.
72-78
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- Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz:
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.
79-82
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- Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles:
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.
83-87
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System Synthesis,
Part 2. Component Based System Synthesis (S5)
- Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards.
88-95
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- Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz:
High-Level Synthesis in Latency Insensitive System Methodology.
96-101
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- Tero Vallius, Juha Röning:
Embedded Object Architecture.
102-107
Electronic Edition (link) BibTeX
- Soujanna Sarkar, Subash G. Chandar:
An Effective Framework for Enabling the Reuse of External Soft IP.
108-113
Electronic Edition (link) BibTeX
Circuits Synthesis,
Part 2. Logic Synthesis (S6)
- Dariusz Kania, Józef Kulisz, Adam Milik:
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.
114-121
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- Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu:
An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS.
122-126
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- Robert Czerwinski, Dariusz Kania:
State Assignment for PAL-based CPLDs.
127-134
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- Vladimir Ciric, Ivan Milentijevic:
Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array.
135-138
Electronic Edition (link) BibTeX
- Krzysztof S. Berezowski, Sarma B. K. Vrudhula:
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series.
139-143
Electronic Edition (link) BibTeX
SS1:
Wireless Sensor Systems,
Part 1. (S7)
- Panu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen:
Design of Transport Triggered Architecture Processors for Wireless Encryption.
144-152
Electronic Edition (link) BibTeX
- C. Siu, Soraya Kasnavi, Kris Iniewski, F. Nabki:
RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing.
153-160
Electronic Edition (link) BibTeX
- Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen:
Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL.
161-164
Electronic Edition (link) BibTeX
- S. Jayapal, S. Ramachandran, R. Bhutada, Yiannos Manoli:
Optimization of Electronic Power Consumption in Wireless Sensor Nodes.
165-169
Electronic Edition (link) BibTeX
- Danielly Cruz, Edna Barros:
Vital Signs Remote Management System for PDAs.
170-175
Electronic Edition (link) BibTeX
Verification Techniques,
Part 1. (S8)
- Tun Li, Dan Zhu, Yang Guo, GongJie Liu, Sikun Li:
MA2TG: A Functional Test Program Generator for Microprocessor Verification.
176-183
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- Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos:
A processor for testing mixed-signal cores in System-on-Chip.
184-191
Electronic Edition (link) BibTeX
- Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional Test Generation Remote Tool.
192-195
Electronic Edition (link) BibTeX
- Daniel Karlsson, Petru Eles, Zebo Peng:
Validation of Embedded Systems Using Formal Method Aided Simulation.
196-201
Electronic Edition (link) BibTeX
Application Specific Architectures,
Part 1. (S9)
- Massimo Rovini, Nicola E. L'Insalata, Francesco Rossi, Luca Fanucci:
VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes.
202-209
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- Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva:
A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.
210-213
Electronic Edition (link) BibTeX
- Jin Hwan Park:
Reconfigurable Parallel Approximate String Matching on FPGAs.
214-217
Electronic Edition (link) BibTeX
- Salvatore Vitabile, Vincenzo Conti, Fulvio Gennaro, Filippo Sorbello:
Efficient MLP Digital Implementation on FPGA.
218-222
Electronic Edition (link) BibTeX
- Michael Freeman, Jim Austin:
Designing a Binary Neural Network Co-processor.
223-227
Electronic Edition (link) BibTeX
- Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari:
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.
227-230
Electronic Edition (link) BibTeX
- Nadia Nedjah, Luiza de Macedo Mourelle:
Massively Parallel Hardware Architecture for Genetic Algorithms.
231-234
Electronic Edition (link) BibTeX
- Oswaldo Cadenas, Graham M. Megson, Daniel Jones:
Implementation of a block based neural branch predictor.
235-238
Electronic Edition (link) BibTeX
- Stanley Hyduke, Vladimir Hahanov, Volodymyr Obrizan, Olesya Guz:
PRUS - Processor Network for Digital Circuit Implementation.
239-242
Electronic Edition (link) BibTeX
- Seppo Virtanen, Jani Paakkulainen, Tero Nurmi:
Capturing Processor Architectures from Protocol Processing Applications: a Case Study.
243-246
Electronic Edition (link) BibTeX
- Zhaojun Wo, Israel Koren, Maciej J. Ciesielski:
Yield-aware Floorplanning.
247-253
Electronic Edition (link) BibTeX
SS1:
Wireless Sensor Systems,
Part 2. (S10)
- Kashif Virk, Jan Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet:
Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes.
254-260
Electronic Edition (link) BibTeX
- Y. Ghiassi, Mohammad M. M. Rad, Mohammad S. Nikjoo, Ali Hesam Mohseni, Babak Hossein Khalaj:
An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval Pattern.
261-266
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- Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen:
Wireless Sensor Network Implementation for Industrial Linear Position Metering.
267-275
Electronic Edition (link) BibTeX
Verification Techniques,
Part 2. (S11)
Application Specific Architectures,
Part 2. (S12)
System Synthesis,
Part 3. High Level Language based System Synthesis (S13)
Reconfigurable Systems,
Part 1. (S14)
Data Management in SoC,
Part 1. (S15)
SS3:
Remonte Educational Tools for Design and Testing,
Part 1 (S16)
Circuits Synthesis,
Part 3. Advanced Logic Synthesis (S17)
Performance Optimization:
Architecture and Tools,
Part 1. (S18)
Copyright © Sat May 16 23:07:29 2009
by Michael Ley (ley@uni-trier.de)
