| 2009 |
|---|
| 11 | EE | Ahmad Al Zahrani,
Andrew Bailey,
Guoyuan Fu,
Jia Di:
Glitch-free design for multi-threshold CMOS NCL circuits.
ACM Great Lakes Symposium on VLSI 2009: 215-220 |
| 2008 |
|---|
| 10 | | Senthilkumar Chinnappa Gounder Periaswamy,
Dale Thompson,
Jia Di:
Ownership Transfer of RFID Tags based on Electronic Fingerprint.
Security and Management 2008: 64-67 |
| 2007 |
|---|
| 9 | EE | Jia Di,
Parag K. Lala:
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.
J. Electronic Testing 23(2-3): 175-192 (2007) |
| 2006 |
|---|
| 8 | EE | Jia Di,
D. P. Vasudevan:
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.
DELTA 2006: 149-156 |
| 7 | EE | Jia Di,
Jiann S. Yuan,
Ronald F. DeMara:
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integration 39(2): 90-112 (2006) |
| 6 | EE | Jia Di,
Jiann S. Yuan:
Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design.
J. Low Power Electronics 2(2): 201-216 (2006) |
| 2005 |
|---|
| 5 | | Jiann S. Yuan,
Jia Di:
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers.
CDES 2005: 218-223 |
| 4 | | Jia Di,
Fengwei Yang:
D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications.
Circuits, Signals, and Systems 2005: 73-78 |
| 3 | EE | Jia Di,
Parag K. Lala,
D. P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.
DFT 2005: 371-379 |
| 2003 |
|---|
| 2 | EE | Jia Di,
Jiann S. Yuan:
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.
ACM Great Lakes Symposium on VLSI 2003: 64-67 |
| 1 | EE | Jia Di,
Jiann S. Yuan,
Ronald F. DeMara:
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
ISVLSI 2003: 260-261 |
