Kwang Sub Yoon

List of publications from the DBLP Bibliography Server - FAQ

2004

5 EE Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim: Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. ISMVL 2004: 198-203

2003

4 EE Yun Cheol Han, Kwang il Kim, Jun Kim, Kwang Sub Yoon: A dual band CMOS VCO with a balanced duty cycle buffer. ACM Great Lakes Symposium on VLSI 2003: 277-280

1999

3 EE Hyuk-Jun Sung, Kwang Sub Yoon: A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) 1999: 553-556

1996

2 EE Jai-Sop Hyun, Kwang Sub Yoon: A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. Great Lakes Symposium on VLSI 1996: 260-

1995

1 Jong Kug Seon, Kwang Sub Yoon: A Precision Output Conductance Model for Analog CMOS Circuit Simulations. ISCAS 1995: 1584-1587

2004
5	EE	Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim: Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. ISMVL 2004: 198-203
2003
4	EE	Yun Cheol Han, Kwang il Kim, Jun Kim, Kwang Sub Yoon: A dual band CMOS VCO with a balanced duty cycle buffer. ACM Great Lakes Symposium on VLSI 2003: 277-280
1999
3	EE	Hyuk-Jun Sung, Kwang Sub Yoon: A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) 1999: 553-556
1996
2	EE	Jai-Sop Hyun, Kwang Sub Yoon: A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. Great Lakes Symposium on VLSI 1996: 260-
1995
1		Jong Kug Seon, Kwang Sub Yoon: A Precision Output Conductance Model for Analog CMOS Circuit Simulations. ISCAS 1995: 1584-1587

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