| 2008 |
|---|
| 5 | EE | Ireneusz Brzozowski,
Andrzej Kos:
A new approach to power estimation and reduction in CMOS digital circuits.
Integration 41(2): 219-237 (2008) |
| 2007 |
|---|
| 4 | | Ireneusz Brzozowski,
Andrzej Kos:
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.
DDECS 2007: 139-144 |
| 2005 |
|---|
| 3 | EE | Ireneusz Brzozowski,
Andrzej Kos:
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.
PATMOS 2005: 456-465 |
| 2001 |
|---|
| 2 | EE | Mariusz Rawski,
Rafal Rzechowski,
Zbigniew Jachna,
Ireneusz Brzozowski:
Practical Aspects of Logic Synthesis Based on Functional Decomposition.
DSD 2001: 38-45 |
| 1999 |
|---|
| 1 | EE | Ireneusz Brzozowski,
Andrzej Kos:
Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity.
EUROMICRO 1999: 1376- |
