| |
| 2007 | ||
|---|---|---|
| 2 | Radoslaw Czarnecki, Stanislaw Deniziak: Resource Constrained Co-synthesis of Self-reconfigurable SOPCs. DDECS 2007: 49-54 | |
| 2003 | ||
| 1 | EE | Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha: An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. DSD 2003: 443-446 |
| 1 | Stanislaw Deniziak | [1] [2] |
| 2 | Krzysztof Sapiecha | [1] |