PARELEC 2006:
Bialystok,
Poland
Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland.
IEEE Computer Society 2006, ISBN 0-7695-2554-7 BibTeX
Invited Papers
Parallel System Architecture
- Bernhard Fechner:
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.
31-36
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- D. Doreen Hephzibah Miriam, T. Srinivasan, R. Deepa:
An Efficient SRA Based Isomorphic Task Allocation Scheme for k - ary n - cube Massively Parallel Processors.
37-42
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- Marcin Gorawski, Michal Gorawski:
Balanced Spatio-Temporal Data Warehouse with R-MVB, STCAT and BITMAP Indexes.
43-48
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- Dajin Wang:
An Algorithm to Embed Hamiltonian Cycles in Crossed Cubes.
49-54
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- Christian Sauer, Matthias Gries, Jörg-Christian Niemann, Mario Porrmann, Michael Thies:
Application-Driven Development of Concurrent Packet Processing Platforms.
55-61
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- Tomasz Madajczak, Henryk Krawczyk:
Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.
62-67
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- Faezeh Montazeri, Mehdi Salmani Jelodar, S. Najmeh Fakhraie, Seid Mehdi Fakhraie:
Evolutionary Multiprocessor Task Scheduling.
68-76
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Parallel System Modeling
Grids
- Christian Kauhaus, Dietmar Fey:
Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach.
111-115
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- Daniel Lamch, Roman Wyrzykowski:
Specification, Analysis and Testing of Grid Environments Using Abstract State Machines.
116-120
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- Adam Kozakiewicz, Andrzej Karbowski:
A Two-Level Approach to Building a Campus Grid.
121-126
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- Jirí Jaros, Milos Ohlídal, Václav Dvorák:
Complexity of Collective Communications on NoCs.
127-133
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- Florin Pop, Ciprian Dobre, Gavril Godza, Valentin Cristea:
A Simulation Model for Grid Scheduling Analysis and Optimization.
133-138
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- T. Srinivasan, N. Dhanasekar, M. Nivedita, R. Dhivyakrishnan, A. A. Azeezunnisa:
Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model.
139-144
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- Stefan Dydel, Krzysztof Benedyczak, Piotr Bala:
Enabling Reconfigurable Hardware Accelerators for the Grid.
145-152
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Automatic Parellelization
Reconfigurable Computing
- Alexander A. Petrovsky, Sergei L. Shkredov:
Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations.
181-186
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- Torsten Mehlan, Jochen Strunk, Torsten Hoefler, Frank Mietke, Wolfgang Rehm:
IRS - A Portable Interface for Reconfigurable Systems.
187-191
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- Sarma Nedunuri, John Y. Cheung, Prakasa Nedunuri:
Design of Low Memory Usage Discrete Wavelet Transform on FPGA Using Novel Diagonal Scan.
192-197
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- A. Pedram, M. R. Jamali, Seid Mehdi Fakhraie, Caro Lucas:
Reconfigurable Parallel Hardware for Computing Local Linear Neuro-Fuzzy Model.
198-201
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- Eryk Laskowski, Marek Tudruj:
Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections.
202-207
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- Oleg Maslennikow, Anatoli Sergyienko:
Mapping DSP Algorithms into FPGA.
208-213
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- Björn Griese, Boris Kettelhoit, Mario Porrmann:
Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors.
214-219
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- Jacek Pierzchlewski, Pawel Sniatala, Blazej Nowakowski, Andrzej Rybarczyk, Wojciech Wencel:
FPGA Chip as a System Master for Hardware Aided Parallel Computing.
220-226
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Performance Monitoring,
Analysis Tools and Methods
- Torsten Hoefler, Carsten Viertel, Torsten Mehlan, Frank Mietke, Wolfgang Rehm:
Assessing Single-Message and Multi-Node Communication Performance of InfiniBand.
227-232
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- Janusz Borkowski, Damian Kopanski, Marek Tudruj:
Parallel Irregular Computations Control Based on Global Predicate Monitoring.
233-238
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- Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Nasser Alzeidi, Mohamed Ould-Khaoua:
Performance Modeling of Fault-Tolerant Circuit-Switched Communication Networks.
239-244
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- Ahmed Yassin Al-Dubai, Imed Romdhani:
A Performance Study of Path Based Multicast Communication Algorithms.
245-250
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- Risto Honkanen:
Nearly-All-Optical Routing in Sparse Optical Tori.
251-256
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- Valérie Fiolet, Eryk Laskowski, Richard Olejnik, Lukasz Masko, Bernard Toursel, Marek Tudruj:
Optimizing Distributed Data Mining Applications Based on Object Clustering Methods.
257-262
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- Changjun Hu, Jing Li, Jue Wang, Yonghong Li, Liang Ding, Jianjiang Li:
Communication Generation for Irregular Parallel Applications.
263-270
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Parallel Numerics
Modeling and Optimization
- Grzegorz M. Wojcik, Wieslaw A. Kaminski:
Pattern Separation in the Model of Mammalian Visual System.
309-312
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- Joanna Kolodziej, Krzysztof Jauernig, Aleksander Cieslar:
HGSNash Strategy as the Decision-Making Method for Water Resource Systems with External Disagreement of Interests.
313-318
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- Wojciech Kwedlo, Krzysztof Bandurski:
A Parallel Differential Evolution Algorithm A Parallel Differential Evolution Algorithm.
319-324
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- Karol Banczyk, Tomasz Boinski, Henryk Krawczyk:
Parallelisation of Genetic Algorithms for Solving University Timetabling Problems.
325-330
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- Jan Kwiatkowski, Marcin Pawlik, Urszula Markowska-Kaczmar, Dariusz Konieczny:
Performance Evaluation of Different Kohenen Network Parallelization Techniques.
331-336
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- Amin Farmahini Farahani, Mehdi Kamal, Mehdi Salmani Jelodar:
Parallel-Genetic-Algorithm-Based HW/SW Partitioning.
337-342
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- R. Deepa, T. Srinivasan, D. Doreen Hephzibah Miriam:
An Efficient Task Scheduling Technique in Heterogeneous Systems Using Self-Adaptive Selection-Based Genetic Algorithm.
343-348
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- Zbigniew J. Czech:
Speeding Up Sequential Simulated Annealing by Parallelization.
349-356
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Image and Signal Processing
- Yunsong Wu, Graham M. Megson:
Parallel Linear Hashtable Motion Estimation Algorithm for Parallel Video Processing.
357-362
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- A. Rodríguez, A. González, Manuel P. Malumbres:
Hierarchical Parallelization of an H.264/AVC Video Encoder.
363-368
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- Marcus Komann, Dietmar Fey:
Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware.
369-373
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- Michael Schmidt, Andreas Loos, Dietmar Fey:
A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems.
374-379
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- Grzegorz Pastuszak:
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding.
380-385
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- Awni Itradat, M. Omair Ahmad, Ali Shatnawi:
A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures.
386-391
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- G. Rubin, K. Bielawski, J. Baszun:
A Hardware Conceptual Prototyping of the Genetic Algorithm to Adaptive IIR Filtering.
392-395
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- Rafal Kapela, Andrzej Rybarczyk:
The Neighboring Pixel Representation for Efficient Binary Image Processing Operations.
396-404
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Applications of Parallel Computing
- Qi Huang, Kaiyu Qin, Wenyong Wang:
A Software Architecture Based on Multi-Agent and Grid Computing for Electric Power System Applications.
405-410
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- Qi Huang, Jianbo Yi, Shi Jing, Ke Huang:
Development of an MPI for Power System Distributed Parallel Computing in Wide Area Network with P2P Technology.
411-416
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- Rajesh K. Bawa, V. Rathish Kumar, Tanu Gupta:
Parallel Mesh Division Algorithm For General Linear Two Point Boundary Value Problems.
417-420
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- Adam Smyk, Marek Tudruj:
Parallel FDTD Computations Optimized by Program Macro Data Flow Graph Redeployment.
421-426
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- Leszek Kasprzyk, Ryszard Nawrowski, Andrzej Tomczewski:
Using a Parallel Virtual Machine to Optimize Lighting Systems.
427-432
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- Qi Huang, Xiaoping Chen, Bingfeng Wang, Ronghai Cai, Kaiyu Qin:
The Concept of Computing on Chip (CoC) for Electric Power System Application.
433-437
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- Luis García, Coromoto León, Gara Miranda, Casiano Rodríguez:
Two-Dimensional Cutting Stock Problem: Shared Memory Parallelizations.
438-443
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- Carmen B. Navarrete, Susana Holgado, Eloy Anguiano:
MPI and Non-MPI Simulations for Epitaxial Surface Growth.
444-447
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- Mariusz Pelc:
Computer Cluster as a Tool in the Continuous Exact State Reconstruction.
448-460
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- Pawel B. Myszkowski:
The Change of State Variables in Global Linearization of Non-Linear State Equation.
454-460
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- Robert Piotr Bycul, Pawel B. Myszkowski:
A Computer Aided Global Linearization of a Non-Linear Electric circuit.
461-465
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- Wojciech Walendziuk, Slawomir Kwieckowski:
The Use of the Dynamic Space Decomposition Algorithm of a Computational Area in Heterogeneous Cluster Computations.
466-469
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- Boguslaw Butrylo:
Distributed Optimization of Temperature Field for Reliable Construction of Electronic Circuits.
470-476
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Copyright © Sat May 16 23:32:33 2009
by Michael Ley (ley@uni-trier.de)
