Sébastien Pillement

2008
17	EE	Julien Lallet, Sébastien Pillement, Olivier Sentieys: Efficient dynamic reconfiguration for multi-context embedded FPGA. SBCCI 2008: 210-215
2007
16	EE	Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
15	EE	Daniel Chillet, Sébastien Pillement, Olivier Sentieys: A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN 2007: 102-107
14	EE	Sébastien Pillement, Raphaël David: Architectures reconfigurable et faible consommation. Réalité ou prospective ? Technique et Science Informatiques 26(5): 595-621 (2007)
2006
13	EE	Jean-Marc Philippe, E. Kinvi-Boh, Sébastien Pillement, Olivier Sentieys: An energy-efficient ternary interconnection link for asynchronous systems. ISCAS 2006
12	EE	Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys: Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. ISQED 2006: 334-339
11		Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny: Clear Stream towards Dynamically Reconfigurable Systems on Chip. ReCoSoC 2006: 98-104
2005
10	EE	Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys: A low-power and high-speed quaternary interconnection link using efficient converters. ISCAS (5) 2005: 4689-4692
9		François Verdier, Jean-Christophe Prévotet, Amine Benkhelifa, Daniel Chillet, Sébastien Pillement: Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC 2005: 71-78
8		Raphaël David, Dominique Lavenier, Sébastien Pillement: Du microprocesseur au circuit FPGA. Une analyse sous l'angle de la reconfiguration. Technique et Science Informatiques 24(4): 395-422 (2005)
2002
7	EE	Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys: A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL 2002: 1058-1067
6	EE	Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys: DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS 2002
5	EE	Sébastien Pillement, Daniel Chillet, Olivier Sentieys: Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED 2002: 388-393
2001
4		Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys: A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC 2001: 51-62
1999
3	EE	Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon: Fast Prototyping: A Case Study - The JPEG Compression Algorithm. IEEE International Workshop on Rapid System Prototyping 1999: 87-
2		S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres: Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. VLSI 1999: 407-414
1996
1		Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon: Concurrent Design of Hardware/Software Dedicated Systems. FPL 1996: 410-414

Coauthor Index

1	Nicolas Abel	[11]
2	Amine Benkhelifa	[9]
3	Gamille Cambon	[2]
4	Gaston Cambon	[1] [3]
5	Daniel Chillet	[4] [5] [6] [7] [9] [15]
6	Raphaël David	[4] [6] [7] [8] [14]
7	Didier Demigny	[11]
8	Frank Hannig	[16]
9	Lounis Kessal	[11]
10	E. Kinvi-Boh	[13]
11	Dmitrij Kissler	[16]
12	Alexey Kupriyanov	[16]
13	Julien Lallet	[16] [17]
14	Dominique Lavenier	[8]
15	Jean-Marc Philippe	[10] [12] [13]
16	Jean-Christophe Prévotet	[9]
17	S. Raimbault	[2]
18	Michel Robert	[1] [2] [3]
19	Gilles Sassatelli	[2]
20	Olivier Sentieys	[4] [5] [6] [7] [10] [12] [13] [15] [16] [17]
21	Jürgen Teich	[16]
22	Lionel Torres	[1] [2] [3]
23	François Verdier	[9]