ICSAMOS 2006:
Samos,
Greece
Georgi Gaydadjiev, C. John Glossner, Jarmo Takala, Stamatis Vassiliadis (Eds.):
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006.
IEEE 2006, ISBN 1-4244-0155-0 BibTeX
Embedded Processors and Architectures
Energy Aware Processors
Design Space Exploration I
- Hartwig Jeschke:
Design Space Expoloration Chip Size Estimation for SOC Design Space Exploration.
56-62
Electronic Edition (link) BibTeX
- Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal:
Profiling Driven Scenarion Detection and Prediction for Multimedia Applications.
63-70
Electronic Edition (link) BibTeX
- Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas:
On the Calibration of Abstract Performance Models for System-level Design Space Exploration.
71-77
Electronic Edition (link) BibTeX
- Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal:
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management.
78-84
Electronic Edition (link) BibTeX
Design Space Exploration II
- Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis:
Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path.
85-92
Electronic Edition (link) BibTeX
- Thilo Streichert, Christian Haubelt, Jürgen Teich:
Multi-Objective Topology Optimization for Networked Embedded Systems.
93-98
Electronic Edition (link) BibTeX
- Rainer Schaffer, Renate Merker:
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism.
99-106
Electronic Edition (link) BibTeX
- Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo:
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA.
107-114
Electronic Edition (link) BibTeX
High Level System Design and Simulation
- Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design.
115-122
Electronic Edition (link) BibTeX
- Hannes Muhr, Roland Höler:
Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression.
123-127
Electronic Edition (link) BibTeX
- Selim Gurun, Ye Wen, Navraj Chohan, Richard Wolski, Chandra Krintz:
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node.
129-136
Electronic Edition (link) BibTeX
- Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya:
Memory-constrained Block Processing Optimization for Synthesis of DSP Software.
137-143
Electronic Edition (link) BibTeX
System and NoC Platforms
Reconfigurable Processors and Applications of ES
Copyright © Sat May 16 23:36:38 2009
by Michael Ley (ley@uni-trier.de)
