The Journal of VLSI Signal Processing, Volume 3

Volume 3, Numbers 1-2, June 1991

• Josef A. Nossek:
  Introduction. 5-6
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• Alfred Fettweis, Gunnar Nitsche:
  Numerical integration of partial differential equations using principles of multidimensional wave digital filters. 7-24
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• Leon O. Chua, L. Yang, K. R. Krieg:
  Signal processing using cellular neural networks. 25-51
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• A. Lumsdaine, John L. Wyatt Jr., Ibrahim M. Elfadel:
  Nonlinear analog networks for image smoothing and segmentation. 53-68
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• J. G. M. C. Whirter, D. S. Broomhead, T. J. Shepherd:
  A systolic array for nonlinear adaptive filtering and pattern recognition. 69-75
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• Jürgen Teich, Lothar Thiele:
  Control generation in the design of processor arrays. 77-92
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• Josef G. Krammer:
  A sorter-based architecture for a parallel implementation of communication intensive algorithms. 93-103
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• Gerhard Fettweis, Heinrich Meyr:
  Feedforward architectures for parallel Viterbi decoding. 105-119
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• Tobias G. Noll:
  Carry-save architectures for high-speed digital signal processing. 121-140
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Volume 3, Number 3, September 1991

• S. Y. Kung:
  Editorial. 147
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• Ed F. Deprettere:
  Introduction. 149
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• S. F. Hsieh, K. J. Ray Liu, Kung Yao:
  Systolic implementations of up/down-dating cholesky factorization using vectorized Gram-Schmidt pseudo orthoganalization. 151-161
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• Marc Moonen, Joos Vandewalle:
  A square root covariance algorithm for constrained recursive least squares estimation. 163-172
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• Hervé Le Verge, Christophe Mauras, Patrice Quinton:
  The ALPHA language and its use for the design of systolic arrays. 173-182
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• Michaël F. X. B. van Swaaij, Jan Rosseel, Francky Catthoor, Hugo De Man:
  Synthesis of ASIC regular arrays for real-time image processing systems. 183-192
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• Ingrid Verbauwhede, Francky Catthoor, Joos Vandewalle, Hugo De Man:
  In-place memory management of algebraic algorithms on application specific ICs. 193-200
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• Jaime H. Moreno, Miguel E. Figueroa, Tomás Lang:
  Linear pseudosystolic array for partitioned matrix algorithms. 201-214
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• Çetin Kaya Koç, Ching Yu Hung:
  Bit-level systolic arrays for modular multiplication. 215-223
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• Anna Antola, Mariagiovanna Sami, Donatella Sciuto:
  Testing and diagnosis ofFFT arrays. 225-236
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• Christian Lengauer, Jingling Xue:
  A systolic array for pyramidal algorithms. 237-257
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Volume 3, Number 4, October 1991

• Vojin G. Oklobdzija, Belle Wei:
  Introduction. 263
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• Brian D. Lee, Vojin G. Oklobdzija:
  Improved CLA scheme with optimized delay. 265-274
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• Xiaoping Huang, Belle W. Y. Wei, Honglu Chen, Yuhai H. Mao:
  High-performance VLSI multiplier with a new redundant binary coding. 283-291
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• Eric M. Schwarz, Michael J. Flynn:
  Cost-efficient high-radix division. 293-305
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• Paul K.-G. Tu, Milos D. Ercegovac:
  Gate array implementation of on-line algorithms for floating-point operations. 307-317
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• Thanos Stouraitis, Alexander Skavantzos:
  Multiplication of complex numbers encoded as polynomials. 319-328
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• Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath:
  New algorithms for reconfiguring VLSI/WSI arrays. 329-344
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• Vibeke Libby:
  Use of window addressable memories for high speed geometrical analysis. 345-355
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