CDES 2006:
Las Vegas,
Nevada,
USA
Hamid R. Arabnia, Mary Mehrnoosh Eshaghian-Wilner (Eds.):
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006.
CSREA Press 2006, ISBN 1-60132-009-4 BibTeX
Algorithms and Hardware Design + VLSI
- Martin Uhl, Werner Held:
On the Management of Object Interrelationships.
3-9 BibTeX
- Sirzat Kahramanli, Suleyman Tosun:
A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization.
10-16 BibTeX
- Mohamed M. Zahran, Manoj Franklin:
RHT: A Context-Based Return Address Predictor.
17-23 BibTeX
- Jinming Ge:
Round-Robin Arbiter Design.
24-28 BibTeX
- Suleyman Tosun, Mahmut T. Kandemir, Hakduran Koc:
Using Task Recomputation During Application Mapping in Parallel Embedded Architectures.
29-35 BibTeX
- Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia:
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs.
36-38 BibTeX
- Jaafar Alghazo:
Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs.
39-45 BibTeX
- Vazgen Karapetyan:
An Algorithm for Yield Improvement via Local Positioning and Resizing.
46-49 BibTeX
- Abby A. Ilumoka, Yeonbum Park:
ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design.
50-56 BibTeX
Circuit Design and Related Issues
Power and Energy
State of the Art Approach for Computer Design
- Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury:
Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates.
101-106 BibTeX
- Kamala Krithivasan, Prahladh Harsha, Muralidhar Talupur:
Communicating Distributed H systems with Simple Splicing Rules.
107-111 BibTeX
- Arun N. Chandorkar, Gurvinder Singh:
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter.
112-117 BibTeX
- Saad Subair, Safaai Deris:
Protein Secondary Structure Prediction Accuracy versus Reduction Methods.
118-124 BibTeX
- Kamala Kritihivasan, Anshu Bhatia, T. S. Chandra:
Simulation of a Turing Machine using EndoII Splicing Rules.
125-129 BibTeX
- Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia:
Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations.
130-134 BibTeX
Memory and Associated Algorithms
High-Performance Systems and Design Issues
- Yajuvendra Nagaonkar, Mark L. Manwaring:
An FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation.
169-174 BibTeX
- Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jian Wang:
New DSP Benchmark based on Selectable Mode Vocoder (SMV).
175-181 BibTeX
- Tsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen, Jia-Shian Wu:
Improving the System Performance by a Dynamic File Prediction Model.
182-188 BibTeX
- Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
189-195 BibTeX
- Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin:
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors.
196-202 BibTeX
- Xiaobo Li, Ke Luo, Xiangdong Cui, Lalin Jiang, Xiaoqiang Ni, Chiyuan Ma, Jingfei Jiang, Huiping Zhou, Zhou Zhou:
A New Processor Architecture with a New Program Driving Method.
203-206 BibTeX
- Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler:
A Configuration Concept for a Massively Parallel FPGA Architecture.
207-212 BibTeX
CNAN'06 - Bio-Inspired and Nano-Scale Integrated Computing
CNAN'06 - Nanotechnology
Late Papers
Copyright © Sat May 16 23:01:00 2009
by Michael Ley (ley@uni-trier.de)
