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Marcus Bednara

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2004
9EEAli Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich: A New Approach for On-line Placement on Reconfigurable Devices. IPDPS 2004
8EEAli Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich: Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS 2004
2003
7EECornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich: A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS 2003: 189
6EECornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi: FPGA designs of parallel high performance GF(2233) multipliers. ISCAS (2) 2003: 268-271
5EEMarcus Bednara, Jürgen Teich: Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. The Journal of Supercomputing 26(2): 149-165 (2003)
2002
4EEMarcus Bednara, Frank Hannig, Jürgen Teich: Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170
3EEMarcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich: Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS 2002
2EEMarcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi: Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) 2002: 797-800
2000
1EEMarcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka: Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP 2000: 299-308

Coauthor Index

1Ali Ahmadinia [8] [9]
2Oliver Beyer [1]
3Christophe Bobda [8] [9]
4M. Daldrup [2] [3]
5Joachim von zur Gathen [2] [3] [6] [7]
6Cornelia Grabbe [6] [7]
7Frank Hannig [4]
8Jamshid Shokrollahi [2] [3] [6] [7]
9Jürgen Teich [1] [2] [3] [4] [5] [6] [7] [8] [9]
10Rolf Wanka [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)