ASAP 2000:
Boston,
MA,
USA
12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA.
IEEE Computer Society 2000, ISBN 0-7695-0716-6 BibTeX
@proceedings{DBLP:conf/asap/2000,
title = {12th IEEE International Conference on Application-Specific Systems,
Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston,
MA, USA},
publisher = {IEEE Computer Society},
year = {2000},
isbn = {0-7695-0716-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote
Video and Multimedia Processors
- Ruby B. Lee:
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures.
3-14
Electronic Edition (link) BibTeX
- Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems.
15-24
Electronic Edition (link) BibTeX
- Wael M. Badawy, Magdy A. Bayoumi:
A Multiplication-Free Parallel Architecture for Affine Transformation.
25-34
Electronic Edition (link) BibTeX
- Marco Antonio Dal Poz, J. Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo:
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications.
35-
Electronic Edition (link) BibTeX
Reconfigurable Computing
- Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube:
Formal Verification for Microprocessors with Extendable Instruction Set.
47-55
Electronic Edition (link) BibTeX
- Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper:
Compiling Image Processing Applications to Reconfigurable Hardware.
56-65
Electronic Edition (link) BibTeX
- Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh:
Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.
66-
Electronic Edition (link) BibTeX
Modeling and Synthesis
- Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis:
High Level Modeling for Parallel Executions of Nested Loop Algorithms.
79-91
Electronic Edition (link) BibTeX
- Andrew Stone, Elias S. Manolakos:
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis.
92-102
Electronic Edition (link) BibTeX
- Wen-Tsong Shiue:
High Level Synthesis for Peak Power Minimization Using ILP.
103-112
Electronic Edition (link) BibTeX
- Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider:
High-Level Synthesis of Nonprogrammable Hardware Accelerators.
113-
Electronic Edition (link) BibTeX
Cryptography
Digital Signal Processing
- Ahmed M. Shams, Magdy A. Bayoumi:
A 108 Gbps, 1.5 GHz 1D-DCT Architecture.
163-172
Electronic Edition (link) BibTeX
- Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang:
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers.
173-184
Electronic Edition (link) BibTeX
- Naraig Manjikian:
A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication.
185-194
Electronic Edition (link) BibTeX
- V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, J. Ashley, R. Karabed:
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.
195-
Electronic Edition (link) BibTeX
Arithmetic
Multiprocessor Systems
Application-Specific Architectures
Design Methodology
Copyright © Sat May 16 22:58:34 2009
by Michael Ley (ley@uni-trier.de)
