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Alexey Kupriyanov

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2007
7EEAlexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
6 Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
5EEAlexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80
2006
4 Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich: A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
3 Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
2005
2 Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
2004
1EEAlexey Kupriyanov, Frank Hannig, Jürgen Teich: High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529

Coauthor Index

1Daniel Chillet [2]
2Hritam Dutta [2] [6]
3Frank Hannig [1] [2] [3] [4] [5] [6] [7]
4Ronan Keryell [2]
5Dmitrij Kissler [3] [4] [5] [6] [7]
6Dirk Koch [4]
7Julien Lallet [7]
8Daniel Menard [2]
9Renate Merker [2] [6]
10Sébastien Pillement [7]
11Bernard Pottier [2] [6]
12Rainer Schaffer [2] [6]
13Olivier Sentieys [2] [7]
14Sebastian Siegel [2] [6]
15Jürgen Teich [1] [2] [3] [4] [5] [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)