| 2007 |
|---|
| 7 | EE | Alexey Kupriyanov,
Frank Hannig,
Dmitrij Kissler,
Jürgen Teich,
Julien Lallet,
Olivier Sentieys,
Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
ARCS 2007: 268-282 |
| 6 | | Hritam Dutta,
Frank Hannig,
Alexey Kupriyanov,
Dmitrij Kissler,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach.
ReCoSoC 2007: 61-68 |
| 5 | EE | Alexey Kupriyanov,
Dmitrij Kissler,
Frank Hannig,
Jürgen Teich:
Efficient event-driven simulation of parallel processor architectures.
SCOPES 2007: 71-80 |
| 2006 |
|---|
| 4 | | Dmitrij Kissler,
Alexey Kupriyanov,
Frank Hannig,
Dirk Koch,
Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
CDES 2006: 189-195 |
| 3 | | Dmitrij Kissler,
Frank Hannig,
Alexey Kupriyanov,
Jürgen Teich:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
ReCoSoC 2006: 31-37 |
| 2005 |
|---|
| 2 | | Frank Hannig,
Hritam Dutta,
Alexey Kupriyanov,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Ronan Keryell,
Bernard Pottier,
Daniel Chillet,
Daniel Menard,
Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC 2005: 27-34 |
| 2004 |
|---|
| 1 | EE | Alexey Kupriyanov,
Frank Hannig,
Jürgen Teich:
High-Speed Event-Driven RTL Compiled Simulation.
SAMOS 2004: 519-529 |
