| 2007 |
|---|
| 9 | | Hritam Dutta,
Frank Hannig,
Alexey Kupriyanov,
Dmitrij Kissler,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach.
ReCoSoC 2007: 61-68 |
| 2006 |
|---|
| 8 | EE | Sebastian Siegel,
Renate Merker:
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.
ASAP 2006: 28-32 |
| 7 | EE | Sebastian Siegel,
Renate Merker:
Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints.
Euro-Par 2006: 1181-1191 |
| 6 | EE | Sebastian Siegel,
Rainer Schaffer,
Renate Merker:
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.
PARELEC 2006: 173-180 |
| 2005 |
|---|
| 5 | EE | Markus Rullmann,
Sebastian Siegel,
Renate Merker:
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching.
IPDPS 2005 |
| 4 | | Frank Hannig,
Hritam Dutta,
Alexey Kupriyanov,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Ronan Keryell,
Bernard Pottier,
Daniel Chillet,
Daniel Menard,
Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC 2005: 27-34 |
| 2004 |
|---|
| 3 | EE | Sebastian Siegel,
Renate Merker:
Optimized Data-Reuse in Processor Arrays.
ASAP 2004: 315-325 |
| 2 | EE | Mathias Kortke,
Jan Müller,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Jürgen Kelber:
A Parallel Hardware-Software System for Signal Processing Algorithms.
PARELEC 2004: 215-220 |
| 1 | EE | Sebastian Siegel,
Renate Merker:
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays.
PARELEC 2004: 85-90 |
