ERSA 2006:
Las Vegas,
Nevada,
USA
Toomas P. Plaks (Ed.):
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2006, Las Vegas, Nevada, USA, June 26-29, 2006.
CSREA Press 2006, ISBN 1-60132-011-6 BibTeX
Worldcomp'06 Keynote
ERSA'06 Keynote
- Chris Rowen:
Using configurable processors for high-efficiency multiple-processor systems.
7-10 BibTeX
Invited Talks
- Maya Gokhale, Christopher Rickett, Justin L. Tripp, Chung Hsu, Ronald Scrofano:
Promises and Pitfalls of Reconfigurable Supercomputing.
11-20 BibTeX
- David L. Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
The Case for High Level Programming Models for Reconfigurable Computers.
21-32 BibTeX
Runtime Resource Management of Reconfigurable Hardware
- Brian Holland, James Greco, Ian A. Troxel, Gabe Barfield, Vikas Aggarwal, Alan D. George:
Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing.
33-41 BibTeX
- Dirk Koch, Matthiaas Koerber, Jürgen Teich:
Searching RC5-Keys with Distributed Reconfigurable Computing.
42-48 BibTeX
- Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal:
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment.
49-55 BibTeX
- Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik:
A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead.
56-62 BibTeX
- Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto:
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture.
63-69 BibTeX
- Markus Koester, Heiko Kalte, Mario Porrmann:
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems.
70-76 BibTeX
- Sebastian Lange, Martin Middendorf:
Cache Architectures for Reconfigurable Hardware.
77-83 BibTeX
- Yvan Eustache, Jean-Philippe Diguet, Milad El Khodary:
RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera.
84-92 BibTeX
Reconfigurable Multiprocessors and Supercomputing
- Craig Ulmer, Adrian Javelo:
Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm.
93-102 BibTeX
- Cao Liang, Jing Ma, Xin-Ming Huang:
An FPGA based Co-Design Architecture for MIMO Lattice Decoders.
103-109 BibTeX
- Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W. van Benthem, Paul M. Heysters:
Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture.
110-116 BibTeX
- Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit:
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture.
117-122 BibTeX
- José:
Delgado-Frias, Jonathan Larson, Mitchell Myjak: Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture.
123-129 BibTeX
- Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano:
A Parametric Study of Scalable Interconnects on FPGAs.
130-135 BibTeX
- Chuan He, Guan Qin, Mi Lu, Wei Zhao:
Group-Alignment based Accurate Floating-Point Summation on FPGAs.
136-142 BibTeX
- Volodymyr V. Kindratenko:
Code Partitioning for Reconfigurable High-Performance Computing: A Case Study.
143-152 BibTeX
Emerging Technologies and Architectures
- Jeoong Sung Park, Hong-Jip Jung, Viktor K. Prasanna:
Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer.
153-163 BibTeX
- Herwin Chan, Patrick Schaumont, Ingrid Verbauwhede:
Process Isolation for Reconfigurable Hardware.
164-170 BibTeX
- Marcel D. van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters:
Hydra: An Energy-efficient and Reconfigurable Network Interface.
171-177 BibTeX
- Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdogan:
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC).
178-183 BibTeX
- Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk:
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation.
184-190 BibTeX
- Joshua Noseworthy, Miriam Leeser:
Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic.
191-197 BibTeX
- Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi:
Differential Reconfiguration Architecture suitable for a Holographic Memory.
198-206 BibTeX
Short Papers
- Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Multi-Mode Operator for SHA-2 Hash Functions.
207-210 BibTeX
- Saumil Merchant, Gregory D. Peterson, Seong Kong:
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks.
211-214 BibTeX
- Yu Bi, Gregory D. Peterson, G. Lee Warren, Robert J. Harrison:
Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation.
215-218 BibTeX
- Mohammad Samie, Gabriel Dragffy, Ebrahim Farjah:
Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems.
219-222 BibTeX
- Xuejun Liang, Qutaibah M. Malluhi:
Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers.
223-226 BibTeX
- Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori:
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
227-230 BibTeX
- Fei Wang, Jack S. N. Jean:
Architectural Support for Runtime 2D Partial Reconfiguration.
231-236 BibTeX
Posters
- Minoru Watanabe, Fuminori Kobayashi:
Logic Synthesis and Place-and-Route Environment for ORGAs.
237-238 BibTeX
- Minoru Watanabe, Fuminori Kobayashi:
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array.
239-240 BibTeX
- Vinay Sriram, David Kearney:
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System.
241-243 BibTeX
- Vinay Sriram, David Kearney:
An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator.
244-246 BibTeX
- Janardhan Singaraju, John A. Chandy:
A Generic Lookup Cache Architecture for Network Processing Applications.
247-248 BibTeX
- Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto:
Synthesis of Object Oriented Models on Reconfigurable Hardware.
249-250 BibTeX
- Alireza Sarvi, Jenny Fan, Reto Stamm:
A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs.
251-252 BibTeX
- Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler:
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.
253-256 BibTeX
Late Papers
- Paul M. Heysters:
The Era of Reconfigurable Computing.
257-264 BibTeX
- Steven Smith:
Dynamic Scheduling and Resource Management in Heterogeneous Computing Environments with Reconfigurable Hardware.
265-271 BibTeX
- Paul M. Heysters:
Coarse-Grained Reconfigurable Computing for Power Aware Applications.
272- BibTeX
Copyright © Sat May 16 23:10:33 2009
by Michael Ley (ley@uni-trier.de)
