ASAP 2006:
Steamboat Springs,
Colorado,
USA
2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA.
IEEE Computer Society 2006, ISBN 0-7695-2682-9 BibTeX
Introduction
Session 1:
Configurable Computing Machines (Invited)
Session 2:
Processing,
Storage and Network On-Chip
- Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede:
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.
15-18
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- Júlio C. B. de Mattos, Stephan Wong, Luigi Carro:
The Molen FemtoJava Engine.
19-22
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- Antoine Scherrer, Antoine Fraboulet, Tanguy Risset:
A Generic Multi-Phase On-Chip Traffic Generation Environment.
23-27
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- Sebastian Siegel, Renate Merker:
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.
28-32
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- Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi:
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.
33-38
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Session 3:
Configurable Processors and Tools (Invited)
Session 4:
Parallel Connection Architectures
Session 5:
Parallel Processing and Arithmetic
- Chuan He, Guan Qin, Mi Lu, Wei Zhao:
An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs.
95-98
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- Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula:
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions.
99-104
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- Tung N. Pham, Earl E. Swartzlander Jr.:
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.
105-108
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- Aasavari Bhave, Eurípides Montagne, Edgar Granados:
Describing Quantum Circuits with Systolic Arrays.
109-113
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- Elie H. Sarraf, Messaoud Ahmed-Ouameur, Daniel Massicotte:
FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System.
114-117
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- Daesun Oh, Keshab K. Parhi:
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.
118-124
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Session 6:
Arithmetic:
Analysis and Implementation
Session 7:
20th Anniversary Review-Array Processors (Invited)
Session 8:
Analysis and Optimizations
- Thomas B. Preuber, Rainer G. Spallek:
Analysis of a Fully-Scalable Digital Fractional Clock Divider.
173-177
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- Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha:
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.
178-181
Electronic Edition (link) BibTeX
- Woo Hyung Lee, Pinaki Mazumder:
Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder.
182-185
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- Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen:
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.
186-190
Electronic Edition (link) BibTeX
- Philippe Clauss, Bénédicte Kenmei:
Polyhedral Modeling and Analysis of Memory Access Profiles.
191-198
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Session 9:
20th Anniversary Review Optimizations and Applications (Invited)
Session 10:
Energy and Performance Optimizations
Session 11:
Video,
Coding and Cryptography
- Thomas Warsaw, Marcin Lukowiak:
Architecture design of an H.264/AVC decoder for real-time FPGA implementation.
253-256
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- Antoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Francky Catthoor, Jordi Carrabina:
Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation.
257-260
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- Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten:
Dynamic-SIMD for lens distortion compensation.
261-264
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- Herwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede:
High Speed Channel Coding Architectures for the Uncoordinated OR Channel.
265-268
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- Youtao Zhang, Jun Yang, Lan Gao:
Efficient Group KeyManagement with Tamper-resistant ISA Extensions.
269-274
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- Guido Bertoni, Luca Breveglieri, Farina Roberto, Francesco Regazzoni:
Speeding Up AES By Extending a 32 bit Processor Instruction Set.
275-282
Electronic Edition (link) BibTeX
Session 12:
Memory and Processor Synthesis
Session 13:
Matrix and Imaging Designs
Session 14:
Cryptographic and Coding Applications
- Neil Smyth, Máire McLoone, John V. McCanny:
An Adaptable And Scalable Asymmetric Cryptographic Processor.
341-346
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- Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat:
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.
347-353
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- Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede:
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation.
354-359
Electronic Edition (link) BibTeX
- Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro:
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation.
360-367
Electronic Edition (link) BibTeX
Copyright © Sat May 16 22:58:33 2009
by Michael Ley (ley@uni-trier.de)
