| |
| 2008 | ||
|---|---|---|
| 2 | EE | Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng: A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320 |
| 2007 | ||
| 1 | EE | Ke Cao, Jiang Hu, Mosong Cheng: Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. VLSI Syst. 15(12): 1332-1340 (2007) |
| 1 | Ke Cao | [1] |
| 2 | Rajesh Garg | [2] |
| 3 | Salman Gopalani | [2] |
| 4 | Jiang Hu | [1] |
| 5 | Sunil P. Khatri | [2] |