| 2008 |
|---|
| 8 | EE | Yongqiang Lu,
Qing Su,
Jamil Kawa:
An innovative Steiner tree based approach for polygon partitioning.
ASP-DAC 2008: 358-363 |
| 2007 |
|---|
| 7 | EE | Yongqiang Lu,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Jun Gu:
An efficient quadratic placement based on search space traversing technology.
Integration 40(3): 253-260 (2007) |
| 2005 |
|---|
| 6 | EE | Yongqiang Lu,
Cliff C. N. Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Register placement for low power clock network.
ASP-DAC 2005: 588-593 |
| 5 | EE | Liang Huang,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Jiang Hu,
Yongqiang Lu:
Clock network minimization methodology based on incremental placement.
ASP-DAC 2005: 99-102 |
| 4 | EE | Yongqiang Lu,
Cliff C. N. Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Navigating registers in placement for clock network minimization.
DAC 2005: 176-181 |
| 3 | EE | Yongqiang Lu,
Chin-Ngai Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions 88-A(12): 3405-3411 (2005) |
| 2004 |
|---|
| 2 | | Changqi Yang,
Xianlong Hong,
Hannah Honghua Yang,
Qiang Zhou,
Yici Cai,
Yongqiang Lu:
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
ISCAS (5) 2004: 81-84 |
| 2003 |
|---|
| 1 | EE | Yongqiang Lu,
Xianlong Hong,
Wenting Hou,
Weimin Wu,
Yici Cai:
Combining clustering and partitioning in quadratic placement.
ISCAS (4) 2003: 720-723 |
