| |
| 2007 | ||
|---|---|---|
| 3 | EE | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. VLSI Syst. 15(10): 1067-1080 (2007) |
| 2006 | ||
| 2 | EE | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Steiner network construction for timing critical nets. DAC 2006: 379-384 |
| 2002 | ||
| 1 | EE | Tao Liu, Qiuyang Li, Yulu Yang: Advanced Baseline: A New MIN with Fault-Tolerance Characteristic. ISPAN 2002: 275-280 |
| 1 | Jiang Hu | [2] [3] |
| 2 | Shiyan Hu | [2] [3] |
| 3 | Peng Li | [2] [3] |
| 4 | Tao Liu | [1] |
| 5 | Yulu Yang | [1] |