| 1999 |
|---|
| 5 | EE | Lun Ye,
Foong-Charn Chang,
Peter Feldmann,
Rakesh Chadha,
Nagaraj Ns,
Frank Cano:
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.
DATE 1999: 658-663 |
| 1992 |
|---|
| 4 | EE | Tom Chanak,
Rakesh Chadha,
Kishore Singhal:
Switched-capacitor simulation models for full-chips verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1363-1371 (1992) |
| 3 | EE | Rakesh Chadha,
Chandramouli Visweswariah,
Chin-Fu Chen:
M3-a multilevel mixed-mode mixed A/D simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 575-585 (1992) |
| 1988 |
|---|
| 2 | EE | Chandramouli Visweswariah,
Rakesh Chadha,
Chin-Fu Chen:
Model Development and Verification for High Level Analog Blocks.
DAC 1988: 376-382 |
| 1987 |
|---|
| 1 | EE | Rakesh Chadha,
Kishore Singhal,
Jiri Vlach,
Ernst Christen,
Milan Vlach:
WATOPT -- An Optimizer for Circuit Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 472-479 (1987) |
