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| 1987 | ||
|---|---|---|
| 2 | EE | Rajiv Kane, Sartaj K. Sahni: A Systolic Design-Rule Checker. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 22-32 (1987) |
| 1984 | ||
| 1 | Rajiv Kane, Sartaj Sahni: VLSI Systems For Design Rule Checks. FSTTCS 1984: 259-278 | |
| 1 | Sartaj Sahni (Sartaj K. Sahni) | [1] [2] |