Joe D. Rutledge

1987
2	EE	Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, Joe D. Rutledge: HSS--A High-Speed Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 601-617 (1987)
1986
1		Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman: Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529

Coauthor Index

1	Zeev Barzilai	[1] [2]
2	J. Lawrence Carter	[1] [2]
3	Vijay S. Iyengar	[1]
4	Indira Nair	[1]
5	Barry K. Rosen	[1] [2]
6	Gabriel M. Silberman	[1]