| 2005 |
|---|
| 13 | EE | James E. Smith,
Ravi Nair:
The Architecture of Virtual Machines.
IEEE Computer 38(5): 32-38 (2005) |
| 2004 |
|---|
| 12 | EE | Harold W. Cain,
Mikko H. Lipasti,
Ravi Nair:
Constraint Graph Analysis of Multithreaded Programs.
J. Instruction-Level Parallelism 6: (2004) |
| 2003 |
|---|
| 11 | EE | Harold W. Cain,
Mikko H. Lipasti,
Ravi Nair:
Constraint Graph Analysis of Multithreaded Programs.
IEEE PACT 2003: 4-14 |
| 2002 |
|---|
| 10 | EE | Ravi Nair:
Effect of increasing chip density on the evolution of computer architectures.
IBM Journal of Research and Development 46(2-3): 223-234 (2002) |
| 1997 |
|---|
| 9 | EE | Ravi Nair,
Martin E. Hopkins:
Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups.
ISCA 1997: 13-25 |
| 1996 |
|---|
| 8 | EE | Pradeep K. Dubey,
Ravi Nair:
Profile-Driven Generation of Trace Samples.
ICCD 1996: 217-224 |
| 7 | | Ravi Nair:
Profiling IBM RS/6000 Applications.
Int. Journal in Computer Simulation 6(1): 101- (1996) |
| 1995 |
|---|
| 6 | EE | Ravi Nair:
Dynamic path-based branch correlation.
MICRO 1995: 15-23 |
| 5 | | Ravi Nair:
Optimal 2-Bit Branch Predictors.
IEEE Trans. Computers 44(5): 698-702 (1995) |
| 1993 |
|---|
| 4 | EE | Lawrence Rauchwerger,
Pradeep K. Dubey,
Ravi Nair:
Measuring limits of parallelism and characterizing its vulnerability to resource constraints.
MICRO 1993: 105-117 |
| 1989 |
|---|
| 3 | EE | Ravi Nair,
C. Leonard Berman,
Peter S. Hauge,
Ellen J. Yoffa:
Generation of performance constraints for layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 860-874 (1989) |
| 1987 |
|---|
| 2 | EE | C. Andrew Neff,
Ravi Nair:
A Ranking Algorithm for MOS Circuit Layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 17-21 (1987) |
| 1 | EE | Ravi Nair:
A Simple Yet Effective Technique for Global Wiring.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 165-172 (1987) |
