Chin Jen Lin
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1987
1
EE
Chin Jen Lin,
Sudhakar M. Reddy
: On Delay Fault Testing in Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 6
(5): 694-703 (1987)
Coauthor
Index
1
Sudhakar M. Reddy
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1
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Sun May 17 03:24:02 2009 by
Michael Ley
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ley@uni-trier.de
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