| 1987 |
|---|
| 3 | EE | Shigeru Takasaki,
Tohru Sasaki,
Nobuyoshi Nomizu,
Nobuhiko Koike,
Kenji Ohmori:
Block-Level Hardware Logic Simulation Machine.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 46-54 (1987) |
| 1986 |
|---|
| 2 | EE | Shigeru Takasaki,
Tohru Sasaki,
Nobuyoshi Nomizu,
Hiroshi Ishikura,
Nobuhiko Koike:
HAL II: a mixed level hardware logic simulation system.
DAC 1986: 581-587 |
| 1984 |
|---|
| 1 | | Tohru Sasaki,
Shunichi Kato,
Nobuyoshi Nomizu,
Hidetoshi Tanaka:
Logic Design Verification Using Automated Test Generation.
ITC 1984: 88-95 |
