T. Watanabe

2002
16	EE	Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda: High density bit-serial FPGA with LUT embedding shift register function. APCCAS (1) 2002: 475-480
15	EE	Jie Huang, K. Kume, A. Saji, M. Nishihashi, T. Watanabe, William L. Martens: Robotic Spatial Sound Localization and Its 3-D Sound Human Interface. CW 2002: 191-200
14	EE	I. Hattori, A. Kamo, T. Watanabe, H. Asai: Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) 2002: 29-32
13	EE	H. Kubota, A. Kamo, T. Watanabe, H. Asai: Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) 2002: 649-552
1999
12	EE	T. Watanabe, A. Mori: RORP: Distributed object relocation protocol for wide area networks. IPCCC 1999: 217-224
11	EE	E. Miuno, T. Abaashi, T. Watanabe: Extracting nonplanar connections in a terminal-vertex graph. ISCAS (6) 1999: 121-124
10	EE	T. Watanabe, H. Asai: Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. ISCAS (6) 1999: 266-269
9	EE	A. Kamo, T. Watanabe, H. Asai: Expanded GMC for transient analysis of transmission line networks. ISCAS (6) 1999: 33-36
8	EE	M. Yamauchi, T. Watanabe: A heuristic algorithm SDS for scheduling with timed Petri nets. ISCAS (6) 1999: 81-84
1997
7	EE	Kazuhiro Ozawa, T. Watanabe, Masayasu Kanke: Fuzzy auto-regressive model and its applications. KES (1) 1997: 112-117
1989
6		C. Jittawiriyanukoon, T. Watanabe, H. Nakanishi, Yoshikazu Tezuka: Approximate Analytic Method for Computer Systems with Multiple Level Concurrent Programs. INFOCOM 1989: 82-90
1987
5	EE	T. Watanabe, S. G. Monanty: On an inclusion-exclusion formula based on the reflection principle. Discrete Mathematics 64(2-3): 281-288 (1987)
4	EE	T. Watanabe, H. Kitazawa, Y. Sugiyama: A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 241-250 (1987)
1986
3	EE	T. Watanabe, T. Masuishi, T. Nishiyama, N. Horie: Knowledge-based optimal IIL generator from conventional logic circuit descriptions. DAC 1986: 608-614
2		K. Murano, Hideo Kuwahara, T. Watanabe, K. Ohta, H. Gambe, T. Gotohda, H. Takaoka: A Processor VLSI for Multiplexing and Circuit Termination Functions - MUX Processor. ICC 1986: 1674-1678
1983
1	EE	T. Watanabe, Makoto Endo, N. Miyahara: A New Automatic Logic Interconnection Verification System for VLSI Design. IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 70-82 (1983)

Coauthor Index

1	T. Abaashi	[11]
2	K. Akahane	[16]
3	H. Asai	[9] [10] [13] [14]
4	Makoto Endo	[1]
5	H. Gambe	[2]
6	T. Gotohda	[2]
7	I. Hattori	[14]
8	N. Horie	[3]
9	Jie Huang	[15]
10	Tsuyoshi Isshiki	[16]
11	C. Jittawiriyanukoon	[6]
12	A. Kamo	[9] [13] [14]
13	Masayasu Kanke	[7]
14	H. Kitazawa	[4]
15	H. Kubota	[13]
16	K. Kume	[15]
17	Hiroaki Kunieda	[16]
18	Hideo Kuwahara	[2]
19	Dongju Li	[16]
20	William L. Martens	[15]
21	T. Masuishi	[3]
22	E. Miuno	[11]
23	N. Miyahara	[1]
24	S. G. Monanty	[5]
25	A. Mori	[12]
26	K. Murano	[2]
27	T. Nakada	[16]
28	H. Nakanishi	[6]
29	M. Nishihashi	[15]
30	T. Nishiyama	[3]
31	Akihisa Ohta	[16]
32	K. Ohta	[2]
33	Kazuhiro Ozawa	[7]
34	A. Saji	[15]
35	I. Sisla	[16]
36	Y. Sugiyama	[4]
37	H. Takaoka	[2]
38	Yoshikazu Tezuka	[6]
39	M. Yamauchi	[8]

Colors in the list of coauthors