| 2008 |
|---|
| 11 | EE | Edith Beigné,
Fabien Clermidy,
Sylvain Miermont,
Pascal Vivet:
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.
NOCS 2008: 129-138 |
| 10 | EE | Ivan Miro Panades,
Fabien Clermidy,
Pascal Vivet,
Alain Greiner:
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.
NOCS 2008: 139-148 |
| 2007 |
|---|
| 9 | EE | Gwen Salaün,
Wendelin Serwe,
Yvain Thonnart,
Pascal Vivet:
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip.
ASYNC 2007: 73-82 |
| 8 | EE | Cedric Koch-Hofer,
Marc Renaudin,
Yvain Thonnart,
Pascal Vivet:
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.
NOCS 2007: 295-306 |
| 7 | EE | Sylvain Miermont,
Pascal Vivet,
Marc Renaudin:
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling.
PATMOS 2007: 556-565 |
| 6 | EE | Anh-Vu Dinh-Duc,
Pascal Vivet,
Alain Clouard:
A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation.
RIVF 2007: 58-64 |
| 5 | EE | Milos Krstic,
Eckhard Grass,
Frank K. Gürkaynak,
Pascal Vivet:
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook.
IEEE Design & Test of Computers 24(5): 430-441 (2007) |
| 2006 |
|---|
| 4 | EE | Edith Beigné,
Pascal Vivet:
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.
ASYNC 2006: 172-183 |
| 2005 |
|---|
| 3 | EE | Edith Beigné,
Fabien Clermidy,
Pascal Vivet,
Alain Clouard,
Marc Renaudin:
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
ASYNC 2005: 54-63 |
| 1999 |
|---|
| 2 | EE | Marc Renaudin,
Pascal Vivet,
Frédéric Robin:
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation.
ASYNC 1999: 135-144 |
| 1998 |
|---|
| 1 | EE | Marc Renaudin,
Pascal Vivet,
Frédéric Robin:
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.
ASYNC 1998: 22-31 |
