| 2008 |
|---|
| 12 | EE | Francesco Centurelli,
Pietro Monsurrò,
Giuseppe Scotti,
Alessandro Trifiletti:
A gain-enhancing technique for very low-voltage amplifiers.
ISCAS 2008: 2282-2285 |
| 2007 |
|---|
| 11 | EE | Francesco Centurelli,
Pietro Monsurrò,
Alessandro Trifiletti:
A distortion model for pipeline Analog-to-Digital converters.
ISCAS 2007: 3387-3390 |
| 10 | EE | Francesco Centurelli,
Luca Giancane,
Mauro Olivieri,
Giuseppe Scotti,
Alessandro Trifiletti:
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
PATMOS 2007: 516-525 |
| 2006 |
|---|
| 9 | EE | Francesco Centurelli,
Pietro Monsurrò,
Alessandro Trifiletti:
A model for the distortion due to switch on-resistance in sample-and-hold circuits.
ISCAS 2006 |
| 8 | EE | Marco Balsi,
Francesco Centurelli,
Piero Marietti,
Giuseppe Scotti,
P. Tommasino,
Alessandro Trifiletti,
G. Valente:
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis.
ISCAS 2006 |
| 2005 |
|---|
| 7 | EE | Francesco Centurelli,
G. Lulli,
Piero Marietti,
Pietro Monsurrò,
Giuseppe Scotti,
Alessandro Trifiletti:
High-speed CMOS-to-ECL pad driver in 0.18µm CMOS.
ISCAS (1) 2005: 448-451 |
| 6 | EE | Francesco Centurelli,
A. Golfarelli,
J. Guinea,
L. Masini,
D. Morigi,
Massimo Pozzoni,
Giuseppe Scotti,
Alessandro Trifiletti:
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. VLSI Syst. 13(2): 191-200 (2005) |
| 2004 |
|---|
| 5 | | Francesco Centurelli,
Massimo Pozzoni,
Giuseppe Scotti,
Alessandro Trifiletti:
A high-speed low-voltage phase detector for clock recovery from NRZ data.
ISCAS (4) 2004: 297-300 |
| 4 | | Francesco Centurelli,
Stefano Costi,
Mauro Olivieri,
Salvatore Pennisi,
Alessandro Trifiletti:
Robust three-state PFD architecture with enhanced frequency acquisition capabilities.
ISCAS (4) 2004: 812-815 |
| 2003 |
|---|
| 3 | EE | Marco Balsi,
Francesco Centurelli,
Giuseppe Scotti,
P. Tommasino,
Alessandro Trifiletti:
An accurate behavioral model of phase detectors for clock recovery circuits.
ISCAS (4) 2003: 636-639 |
| 2000 |
|---|
| 2 | EE | Andrea Pallotta,
Francesco Centurelli,
Alessandro Trifiletti:
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.
ISLPED 2000: 67-72 |
| 1998 |
|---|
| 1 | | Andrea Pallotta,
Francesco Centurelli,
Francesco Loriga,
Alessandro Trifiletti:
A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology.
SYBEN 1998: 183-190 |
