| |
| 1993 | ||
|---|---|---|
| 2 | S. Bapat, James P. Cohoon: A Parallel VLSI Circuit Layout Methodology. VLSI Design 1993: 236-241 | |
| 1986 | ||
| 1 | EE | S. Bapat, G. Venkatesh: Reasoning about digital systems using temporal logic. DAC 1986: 215-219 |
| 1 | James P. Cohoon | [2] |
| 2 | G. Venkatesh | [1] |