| 2008 |
|---|
| 17 | | Masaya Yoshikawa,
Hidekazu Terai:
Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization.
GEM 2008: 135-139 |
| 16 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Route selection algorithm based on integer operation Ant Colony Optimization.
IRI 2008: 17-21 |
| 2007 |
|---|
| 15 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Architecture for high-speed Ant Colony Optimization.
IRI 2007: 1-5 |
| 14 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption.
JACIII 11(2): 168-175 (2007) |
| 2006 |
|---|
| 13 | | Masaya Yoshikawa,
Hidekazu Terai:
Co-evolutionary robotics using two kinds of neural networks.
CAINE 2006: 330-334 |
| 12 | | Masaya Yoshikawa,
Masahiro Fukui,
Hidekazu Terai:
Immune Algorithm Processor.
Computers and Their Applications 2006: 13-18 |
| 11 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing.
SERA 2006: 95-100 |
| 10 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation.
JACIII 10(1): 112-120 (2006) |
| 2005 |
|---|
| 9 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Performance driven placement technique based on collaboration of software and hardware.
Congress on Evolutionary Computation 2005: 1570-1575 |
| 8 | EE | Masaya Yoshikawa,
Hidekazu Terai:
A Hierarchical Parallel Placement Technique based on Genetic Algorithm.
ISDA 2005: 302-307 |
| 7 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique.
SERA 2005: 130-136 |
| 2004 |
|---|
| 6 | | Tetsuya Imai,
Masaya Yoshikawa,
Hidekazu Terai,
Hironori Yamauchi:
VLSI processor architecture for real-time GA processing and PE-VLSI design.
ISCAS (3) 2004: 625-628 |
| 1994 |
|---|
| 5 | EE | Hidekazu Terai,
Kazutoshi Gemma,
Yohsuke Nagao,
Yasuo Satoh,
Yasuhiro Ohno:
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1.
DAC 1994: 262-269 |
| 1991 |
|---|
| 4 | EE | Hidekazu Terai,
Fumio Goto,
Katsuro Wakai,
Tokinori Kozawa,
Mitsugu Edagawa,
Satoshi Hososaka,
Masahiro Hashimoto:
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers.
DAC 1991: 193-198 |
| 1988 |
|---|
| 3 | EE | Yasushi Ogawa,
Hidekazu Terai,
Tokinori Kozawa:
Automatic Layout Procedures for Serial Routing Devices.
DAC 1988: 642-645 |
| 1986 |
|---|
| 2 | EE | Yasushi Ogawa,
Tatsuki Ishii,
Yoichi Shiraishi,
Hidekazu Terai,
Tokinori Kozawa,
Kyoji Yuyama,
Kyoji Chiba:
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs.
DAC 1986: 404-410 |
| 1985 |
|---|
| 1 | EE | Hidekazu Terai,
Michiyoshi Hayase,
Tokinori Kozawa:
A routing procedure for mixed array of custom macros and standard cells.
DAC 1985: 503-508 |
