The Journal of VLSI Signal Processing, Volume 16

Volume 16, Number 1, May 1997

• Keshab K. Parhi, Takao Nishitani, Hironori Yamauchi:
  Guest Editors' Introduction. 5-7
  Electronic Edition (link) BibTeX
• Won Namgoong, Teresa H. Y. Meng:
  A Low-Power Encoder For Pyramid Vector Quantization of Subband Coefficients. 9-23
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• Masahiro Iwadare, Hideto Takano, Yoshitaka Shibuya, Hideki Sakamoto, Takeshi Kuwajima, Osamu Kitabatake, Naoko Kobayashi:
  A Single-Chip MPEG/Audio Decoder LSI Based on a Compact Decoding Algorithm. 25-30
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• Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch:
  An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. 31-40
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• David W. Trainor, Roger F. Woods, John V. McCanny:
  Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". 41-55
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• Kazuhito Ito, Keshab K. Parhi:
  A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. 57-72
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• Vojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr:
  Compiled Simulation of Programmable DSP Architectures. 73-80
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• Anissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal:
  Efficient Implementation Methodology of Fast FIR Filtering Algorithms on DSP. 81-103
  Electronic Edition (link) BibTeX

Volume 16, Numbers 2-3, June 1997

• Eby G. Friedman:
  High Performance Clock Distribution Networks. 113-116
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• Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli:
  Clock Skew Optimization for Peak Current Reduction. 117-130
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• Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III:
  Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. 131-147
  Electronic Edition (link) BibTeX
• José Luis Neves, Eby G. Friedman:
  Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. 149-161
  Electronic Edition (link) BibTeX
• Joe G. Xi, Wayne Wei-Ming Dai:
  Useful-Skew Clock Routing with Gate Sizing for Low Power Design. 163-179
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• Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela:
  Clock Distribution Methodology for PowerPC^TM Microprocessors. 181-189
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• David J. Hathaway, Rafik R. Habra, Erich C. Schanzenbach, Sara J. Rothman:
  Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology. 191-198
  Electronic Edition (link) BibTeX
• Andrew B. Kahng, Chung-Wen Albert Tsao:
  Practical Bounded-Skew Clock Routing. 199-215
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• Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss:
  A Clock Methodology for High-Performance Microprocessors. 217-224
  Electronic Edition (link) BibTeX
• Stuart K. Tewksbury, Lawrence A. Hornak:
  Optical Clock Distribution in Electronic Systems. 225-246
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• Kris Gaj, Eby G. Friedman, Marc J. Feldman:
  Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. 247-276
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