The Journal of VLSI Signal Processing, Volume 8

Volume 8, Number 1, February 1994

• Earl E. Swartzlander Jr.:
  Editorial. 5
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• Michael D. Godfrey:
  Guest editor's introduction. 7
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• Carver Mead:
  Scaling of MOS technology to submicrometer feature sizes. 9-25
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• Eric A. Vittoz:
  Analog VLSI signal processing: Why, where, and how? 27-44
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• Boyd Fowler, Abbas El Gamal:
  Pulse-modulated analog neuron circuits. 45-51
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• D. L. Grundy:
  A computational approach to VLSI analog design. 53-60
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• Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen:
  Analog VLSI for robot path planning. 61-73
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• Aleksandra Pavasovic, Andreas G. Andreou, Charles R. Westgate:
  Characterization of subthreshold MOS mismatch in transistors for VLSI systems. 75-85
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Volume 8, Number 2, June 1994

• Lothar Thiele, Edward Chow:
  Guest editors' introduction. 95
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• Shiv Prakash, Alice C. Parker:
  Synthesis of application-specific multiprocessor systems including memory components. 97-116
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• Miodrag Potkonjak, Jan M. Rabaey:
  Optimizing throughput and resource utilization using pipelining: Transformation based approach. 117-130
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• Phu Hoang, Jan M. Rabaey:
  A CAD environment for Real-time DSP implementations on multiprocessors. 131-150
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• Stephen E. McQuillan, John V. McCanny:
  Fast VLSI algorithms for division and square root. 151-168
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• Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr:
  High-speed VLSI architectures for soft-output viterbi decoding. 169-181
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• Stan Knight, Danny Chin, Herb Taylor, J. Peters:
  The sarnoff engine: A massively parallel computer for high definition system simulation. 183-199
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Volume 8, Number 3, October 1994

• Graham A. Jullien:
  Guest editor's introduction. 207-208
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• Howard C. Card, Christian R. Schneider, Roland S. Schneider:
  Learning capacitive weights in analog CMOS neural networks. 209-225
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• Calvin Plett, Miles A. Copeland:
  Self-tuned continuous-time notch filters. 227-240
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• T. C. Davies, Dhamin Al-Khalili, V. Szwarc:
  A floating-point systolic array processing element with serial communication and built-in self-test. 241-251
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• V. Szwarc, L. Desormeaux, W. Wong, C. P. S. Yeung, C. H. Chan, Tad A. Kwasniewski:
  A chip set for pipeline and parallel pipeline FFT architectures. 253-265
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• Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu:
  Testing of programmable analog neural network chips. 267-282
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• Marc Moonen:
  Implementing the square-root information Kalman filter on a Jacobi-type systolic array. 283-291
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• Patrick Fitzpatrick:
  On fault tolerant matrix decomposition. 293-303
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• Subir Bandyopadhyay, Graham A. Jullien, Abhijit Sengupta:
  A fast VLSI systolic array for large modulus residue addition. 305-318
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