| |
| 2003 | ||
|---|---|---|
| 1 | EE | Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 |
| 1 | Gerd Ascheid | [1] |
| 2 | Malte Doerper | [1] |
| 3 | Tim Kogel | [1] |
| 4 | Rainer Leupers | [1] |
| 5 | Heinrich Meyr | [1] |
| 6 | Andreas Wieferink | [1] |