| 2004 |
|---|
| 3 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Mario Steinert,
Gunnar Braun,
Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation.
DATE 2004: 156-160 |
| 2 | | Mario Steinert,
Stefano Marsili:
Power consumption optimization for low latency Viterbi Decoder.
ISCAS (2) 2004: 377-380 |
| 2002 |
|---|
| 1 | EE | S. R. Meier,
Mario Steinert,
S. Buch:
Testability of path history memories with register-exchange architecture used in Viterbi-decoders.
ISCAS (3) 2002: 165-168 |
