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Mario Steinert

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2004
3EEOliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl: RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160
2 Mario Steinert, Stefano Marsili: Power consumption optimization for low latency Viterbi Decoder. ISCAS (2) 2004: 377-380
2002
1EES. R. Meier, Mario Steinert, S. Buch: Testability of path history memories with register-exchange architecture used in Viterbi-decoders. ISCAS (3) 2002: 165-168

Coauthor Index

1Gerd Ascheid [3]
2Gunnar Braun [3]
3S. Buch [1]
4Anupam Chattopadhyay [3]
5Rainer Leupers [3]
6Stefano Marsili [2]
7S. R. Meier [1]
8Heinrich Meyr [3]
9Achim Nohl [3]
10Oliver Schliebusch [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)