18. RSP 2007:
Porto Alegre,
RS,
Brazil
18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil.
IEEE Computer Society 2007, ISBN 978-0-7695-2834-2 BibTeX
Session 1:
Co-design
- Andre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana:
Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass.
3-9
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- Kenneth B. Kent, Beatriz C. Iaderoza, Micaela Serra:
Codesign of a Computationally Intensive Problem in GF(3).
10-16
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- Fernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López:
Unified Inter-Communication Architecture for Systems-on-Chip.
17-26
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Session 2:
HW Performance
Session 3:
Short Papers FPGA - Applications
- Everton Carara, Aline Mello, Fernando Moraes:
Communication Models in Networks-on-Chip.
57-60
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- Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle:
A Lightweight Framework for Runtime Reconfigurable System Prototyping.
61-64
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- V. Mariatos, K. Adaos, George Alexiou:
Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System.
65-68
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- Júlio C. B. de Mattos, Antonio Carlos Schneider Beck, Luigi Carro:
Object-Oriented Reconfiguration.
69-74
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Session 4:
Formal Specification
Session 5:
Prototyping and Development Methodologies and Tools
- Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt:
A Tailored Design Partitioning Method for Hardware Emulation.
99-105
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- Jérôme Hugues, Bechir Zalila, Laurent Pautet, Fabrice Kordon:
Rapid Prototyping of Distributed Real-Time Embedded Systems Using the AADL and Ocarina.
106-112
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- Katalin Popovici, Xavier Guerin, Frédéric Rousseau, Pier Stanislao Paolucci, Ahmed Amine Jerraya:
Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels.
113-122
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Session 6:
Testing
Session 7:
Short Papers - HW Performance,
Co-Design and Tool
- Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes:
Architectural Issues in Homogeneous NoC-Based MPSoC.
139-142
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- Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch:
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.
143-149
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- Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick Wolf:
Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers.
150-156
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Session 8:
Short Papers - Formal Specification
Session 9:
Applications
- X. H. Tian, Thinh M. Le, B. L. Ho, Yong Lian:
A CABAC Encoder Design of H.264/AVC with RDO Support.
167-173
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- Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin:
FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
174-180
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- David Matschulat, César A. M. Marcon, Fabiano Hessel:
ER-EDF: A QoS Scheduler for Real-Time Embedded Systems.
181-188
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Session 10:
FPGA and SW Algorithms
- Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
189-194
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- Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya:
Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes.
195-201
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- Chanik Park, Wonmoon Cheon, Yangsup Lee, Myoung-Soo Jung, Wonhee Cho, Hanbin Yoon:
A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications.
202-208
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Copyright © Sat May 16 23:36:06 2009
by Michael Ley (ley@uni-trier.de)