Emre Özer

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16EEEmre Özer, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner: Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. SAMOS 2008: 12-22
15EEEmre Özer, Andy Nisbet, David Gregg: A stochastic bitwidth estimation technique for compact and low-power custom processors. ACM Trans. Embedded Comput. Syst. 7(3): (2008)
14EEEmre Özer, Stuart Biles: Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor. Asia-Pacific Computer Systems Architecture Conference 2007: 376-386
13EEEmre Özer, Alastair Reid, Stuart Biles: Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor. SBAC-PAD 2007: 37-44
12EEMrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee: Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. ARCS 2006: 283-297
11EEDong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee: Reducing energy of virtual cache synonym lookup using bloom filters. CASES 2006: 179-189
10EEYunhe Shi, Emre Özer, David Gregg: Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors. ISCIS 2006: 248-257
9EEOwen Callanan, Andy Nisbet, Emre Özer, James Sexton, David Gregg: FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic. IPDPS 2005
8EEEmre Özer, Resit Sendag, David Gregg: Multiple-Valued Caches for Power-Efficient Embedded Systems. ISMVL 2005: 126-131
7EEEmre Özer, Thomas M. Conte: High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. IEEE Trans. Parallel Distrib. Syst. 16(12): 1132-1142 (2005)
6EEEmre Özer, Andy Nisbet, David Gregg: Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors. CC 2004: 250-264
5EEEmre Özer, Andy Nisbet, David Gregg: Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power Using Optimizing Compiler Techniques. Euro-Par 2004: 318-327
4EEEmre Özer, Andy Nisbet, David Gregg: Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs. FCCM 2004: 273-274
3EEEmre Özer, Thomas M. Conte, Saurabh Sharma: Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. HiPC 2001: 192-203
2EEEmre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte: A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT 1998: 136-141
1EEEmre Özer, Sanjeev Banerjia, Thomas M. Conte: Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. MICRO 1998: 308-315

Coauthor Index

1Sanjeev Banerjia [1] [2]
2Stuart Biles [11] [12] [13] [14] [16]
3Owen Callanan [9]
4Thomas M. Conte [1] [2] [3] [7]
5Ronald G. Dreslinski [16]
6Krisztián Flautner [16]
7Mrinmoy Ghosh [11] [12]
8David Gregg [4] [5] [6] [8] [9] [10] [15]
9Matthew D. Jennings [2]
10Hsien-Hsin S. Lee [11] [12]
11Kishore N. Menezes [2]
12Trevor N. Mudge [16]
13Andy Nisbet (Andrew Nisbet) [4] [5] [6] [9] [15]
14Alastair David Reid (Alastair D. Reid, Alastair Reid) [13]
15Sumedh W. Sathaye [2]
16Resit Sendag [8]
17James Sexton [9]
18Saurabh Sharma [3]
19Yunhe Shi [10]
20Dong Hyuk Woo [11]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)