38. MICRO 2005: Barcelona, Spain

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain. IEEE Computer Society 2005, ISBN 0-7695-2440-0 BibTeX

Introduction

Message from the General Chairs.
Electronic Edition (link) BibTeX
Message from the Program Co-Chairs.
Electronic Edition (link) BibTeX

Keynote I

James A. Kahle:
The Cell Processor Architecture. 3
Electronic Edition (link) BibTeX

Session I: Register File and Memory System

David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt:
How to Fake 1000 Registers. 7-18
Electronic Edition (link) BibTeX
Stephen Hines, Gary S. Tyson, David B. Whalley:
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. 19-29
Electronic Edition (link) BibTeX
Arvind Krishnaswamy, Rajiv Gupta:
Efficient Use of Invisible Registers in Thumb Code. 30-42
Electronic Edition (link) BibTeX

Session II: Processor Design and Optimization

Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt:
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. 43-54
Electronic Edition (link) BibTeX
Pierre Salverda, Craig B. Zilles:
A Criticality Analysis of Clustering in Superscalar Processors. 55-66
Electronic Edition (link) BibTeX
Matt T. Yourst, Kanad Ghose:
Incremental Commit Groups for Non-Atomic Trace Processing. 67-80
Electronic Edition (link) BibTeX

Session III: Multithreading / CMP

Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita:
Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities. 81-92
Electronic Edition (link) BibTeX
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham:
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor. 93-104
Electronic Edition (link) BibTeX
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August:
Automatic Thread Extraction with Decoupled Software Pipelining. 105-118
Electronic Edition (link) BibTeX

Session IV: Compilers and Dynamic Optimization

Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe:
Exploiting Vector Parallelism in Software Pipelined Loops. 119-129
Electronic Edition (link) BibTeX
Michael D. Bond, Kathryn S. McKinley:
Continuous Path and Edge Profiling. 130-140
Electronic Edition (link) BibTeX
David Hiniker, Kim M. Hazelwood, Michael D. Smith:
Improving Region Selection in Dynamic Optimization Systems. 141-154
Electronic Edition (link) BibTeX

Keynote II

Norman P. Jouppi:
The Future Evolution of High-Performance Microprocessors. 155
Electronic Edition (link) BibTeX

Session V: Memory Disambiguation and Optimization

Tingting Sha, Milo M. K. Martin, Amir Roth:
Scalable Store-Load Forwarding via Store Queue Index Prediction. 159-170
Electronic Edition (link) BibTeX
Sam S. Stone, Kevin M. Woley, Matthew I. Frank:
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding. 171-182
Electronic Edition (link) BibTeX
Yuan Chou, Lawrence Spracklen, Santosh G. Abraham:
Store Memory-Level Parallelism Optimizations for Commercial Applications. 183-196
Electronic Edition (link) BibTeX

Session VI: Processor Design

Fred A. Bower, Daniel J. Sorin, Sule Ozev:
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. 197-208
Electronic Edition (link) BibTeX
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau:
uComplexity: Estimating Processor Design Effort. 209-218
Electronic Edition (link) BibTeX
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke:
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System. 219-232
Electronic Edition (link) BibTeX

Session VII: Speculation

Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. 233-244
Electronic Edition (link) BibTeX
Meyrem Kirman, Nevin Kirman, José F. Martínez:
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. 245-256
Electronic Edition (link) BibTeX
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou:
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. 257-270
Electronic Edition (link) BibTeX

Session VIII: Power, Temperature and Fault Management

Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks:
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. 271-282
Electronic Edition (link) BibTeX
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail:
Thermal Management of On-Chip Caches Through Power Density Minimization. 283-293
Electronic Edition (link) BibTeX
Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar:
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. 294-304
Electronic Edition (link) BibTeX
Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross:
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation. 305-318
Electronic Edition (link) BibTeX

Session IX: Processor Architecture and Programming

Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu:
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense. 319-330
Electronic Edition (link) BibTeX
Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen:
The TM3270 Media-Processor. 331-342
Electronic Edition (link) BibTeX
Jayanth Gummaraju, Mendel Rosenblum:
Stream Programming on General-Purpose Processors. 343-354
Electronic Edition (link) BibTeX
Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa:
Shader Performance Analysis on a Modern GPU Architecture. 355-364
Electronic Edition (link) BibTeX