20. ISCA 1993:
San Diego, CA, USA
Lubomir Bic (Ed.):
Proceedings of the 20th Annual International Symposium on Computer Architecture. San Diego,
CA,
May 1993. IEEE Computer Society Press,
1993
- Robert Cypher, Alex Ho, Smaragda Konstantinidou, Paul Messina:
Architectural Requirements of Parallel Scientific Applications with Explicit Communication.
2-13 BibTeX
- Edward Rothberg, Jaswinder Pal Singh, Anoop Gupta:
Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors.
14-25 BibTeX
- David Nagle, Richard Uhlig, Timothy J. Stanley, Stuart Sechrest, Trevor N. Mudge, Richard B. Brown:
Design Tradeoffs for Software-Managed TLBs.
27-38 BibTeX
- Jerome C. Huck, Jim Hays:
Architectural Support for Translation Table Management in Large Address Space Machines.
39-50 BibTeX
- Pei Cao, Swee Boon Lim, Shivakumar Venkataraman, John Wilkes:
The TickerTAIP Parallel RAID Architecture.
52-63 BibTeX
- Daniel Stodolsky, Garth A. Gibson, Mark Holland:
Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays.
64-75 BibTeX
- Jai Menon, Jim Cortney:
The Architecture of a Fault-Tolerant Cached RAID Controller.
76-86 BibTeX
- Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström:
The Detection and Elimination of Useless Misses in Multiprocessors.
88-97 BibTeX
- Alan L. Cox, Robert J. Fowler:
Adaptive Cache Coherency for Detecting Migratory Shared Data.
98-108 BibTeX
- Per Stenström, Mats Brorsson, Lars Sandberg:
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing.
109-118 BibTeX
- Carl A. Waldspurger, William E. Weihl:
Register Relocation: Flexible Contexts for Multithreading.
120-130 BibTeX
- Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Multiple Threads in Cyclic Register Windows.
131-142 BibTeX
- Sandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel:
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology.
144-155 BibTeX
- David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt:
Mechanisms for Cooperative Shared Memory.
156-167 BibTeX
- André Seznec:
A Case for Two-Way Skewed-Associative Caches.
169-178 BibTeX
- Anant Agarwal, Steven D. Pudar:
Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches.
179-190 BibTeX
- Norman P. Jouppi:
Cache Write Policies and Performance.
191-201 BibTeX
- Eric L. Boyd, Edward S. Davidson:
Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240.
203-212 BibTeX
- David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner:
The Cedar System and an Initial Performance Study.
213-223 BibTeX
- Michael D. Noakes, Deborah A. Wallach, William J. Dally:
The J-Machine Multicomputer: An Architectural Evaluation.
224-235 BibTeX
- John Bunda, Donald S. Fussell, Roy M. Jenevein, William C. Athas:
16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors.
237-246 BibTeX
- Tokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu:
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures.
247-256 BibTeX
- Tse-Yu Yeh, Yale N. Patt:
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History.
257-266 BibTeX
- Luiz André Barroso, Michel Dubois:
The Performance of Cache-Coherent Ring-based Multiprocessors.
268-277 BibTeX
- Dean M. Tullsen, Susan J. Eggers:
Limitations of Cache Prefetching on a Bus-Based Multiprocessor.
278-288 BibTeX
- Maurice Herlihy, J. Eliot B. Moss:
Transactional Memory: Architectural Support for Lock-Free Data Structures.
289-300 BibTeX
- Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally:
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5.
302-313 BibTeX
- Takeshi Horie, Kenichi Hayashi, Toshiyuki Shimizu, Hiroaki Ishihata:
Improving AP1000 Parallel Computer Performance with Message Communication.
314-325 BibTeX
- Wei-Chung Hsu, James E. Smith:
Performance of Cached DRAM Organizations in Vector Supercomputers.
327-336 BibTeX
- Q. S. Gao:
The Chinese Remainder Theorem and the Prime Memory System.
337-340 BibTeX
- André Seznec, Jacques Lenfant:
Odd Memory Systems May be Quite Interesting.
341-350 BibTeX
- Rajendra V. Boppana, Suresh Chalasani:
A Comparison of Adaptive Wormhole Routing Algorithms.
351-360 BibTeX
Copyright © Sat May 16 23:24:56 2009
by Michael Ley (ley@uni-trier.de)
