2009 | ||
---|---|---|
39 | EE | André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings Springer 2009 |
38 | EE | Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi: CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA 2009: 289-300 |
2008 | ||
37 | EE | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 |
36 | EE | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10 |
35 | EE | Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer: Adaptive insertion policies for managing shared caches. PACT 2008: 208-219 |
34 | EE | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer: Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) |
2007 | ||
33 | EE | Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler: Late-binding: enabling unordered load-store queues. ISCA 2007: 347-357 |
32 | EE | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer: Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 |
31 | EE | Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag: Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro 27(6): 14-24 (2007) |
2005 | ||
30 | EE | Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt: The Soft Error Problem: An Architectural Perspective. HPCA 2005: 243-247 |
29 | EE | Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan: Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA 2005: 532-543 |
2004 | ||
28 | EE | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt: Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. ISCA 2004: 264-275 |
27 | EE | Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt: Cache Scrubbing in Microprocessors: Myth or Necessity? PRDC 2004: 37-42 |
26 | EE | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt: Reducing the Soft-Error Rate of a High-Performance Microprocessor. IEEE Micro 24(6): 30-37 (2004) |
2003 | ||
25 | EE | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. MICRO 2003: 29-42 |
24 | EE | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin: Measuring Architectural Vulnerability Factors. IEEE Micro 23(6): 70-75 (2003) |
2002 | ||
23 | EE | Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb: A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. ASPLOS 2002: 223-234 |
22 | EE | Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer: Loose Loops Sink Chips. HPCA 2002: 299-310 |
21 | EE | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec: Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281- |
20 | EE | Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson: Performance Simulation Tools. IEEE Computer 35(2): 38-39 (2002) |
19 | EE | Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan: Asim: A Performance Model Framework. IEEE Computer 35(2): 68-76 (2002) |
2000 | ||
18 | EE | Harish Patil, Joel S. Emer: Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. HPCA 2000: 251- |
1999 | ||
17 | EE | Timothy Sherwood, Brad Calder, Joel S. Emer: Reducing cache misses using hardware and software page placement. International Conference on Supercomputing 1999: 155-164 |
16 | EE | Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi: The Use of Multithreading for Exception Handling. MICRO 1999: 219-229 |
1998 | ||
15 | EE | Joel S. Emer, Douglas W. Clark: A Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints 1998: 274-283 |
14 | EE | Joel S. Emer, Douglas W. Clark: Retrospective: Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints 1998: 37-38 |
13 | EE | George Z. Chrysos, Joel S. Emer: Memory Dependence Prediction Using Store Sets. ISCA 1998: 142-153 |
1997 | ||
12 | EE | Joel S. Emer, Nicholas C. Gloy: A Language for Describing Predictors and Its Application to Automatic Synthesis. ISCA 1997: 304-314 |
11 | EE | Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen: Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ACM Trans. Comput. Syst. 15(3): 322-354 (1997) |
1996 | ||
10 | EE | Brad Calder, Dirk Grunwald, Joel S. Emer: Predictive Sequential Associative Cache. HPCA 1996: 244-253 |
9 | EE | Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ISCA 1996: 191-202 |
8 | Joel S. Emer: Incremental Versus Revolutionary Research. ACM Comput. Surv. 28(4es): 27 (1996) | |
1995 | ||
7 | EE | Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer: Instruction Fetching: Coping with Code Bloat. ISCA 1995: 345-356 |
6 | EE | Brad Calder, Dirk Grunwald, Joel S. Emer: A system level perspective on branch architecture performance. MICRO 1995: 199-206 |
1989 | ||
5 | EE | K. K. Ramakrishnan, Joel S. Emer: Performance Analysis of Mass Storage Service Alternatives for Distributed Systems. IEEE Trans. Software Eng. 15(2): 120-133 (1989) |
1988 | ||
4 | Joel S. Emer, K. K. Ramakrishnan: Performance Considerations for Distributed Services: A Case Study: Mass Storage. ICDCS 1988: 289-297 | |
1986 | ||
3 | EE | Joel S. Emer, K. K. Ramakrishnan: Design analysis of a heterogeneous distributed system. ACM SIGOPS European Workshop 1986 |
1985 | ||
2 | EE | Douglas W. Clark, Joel S. Emer: Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement ACM Trans. Comput. Syst. 3(1): 31-62 (1985) |
1984 | ||
1 | Joel S. Emer, Douglas W. Clark: A Characterization of Processor Performance in the VAX-11/780. ISCA 1984: 301-310 |