| 2001 |
|---|
| 4 | EE | Matt Postiff,
David Greene,
Steven E. Raasch,
Trevor N. Mudge:
Integrating superscalar processor components to implement register caching.
ICS 2001: 348-357 |
| 2000 |
|---|
| 3 | EE | Matt Postiff,
David Greene,
Trevor N. Mudge:
The store-load address table and speculative register promotion.
MICRO 2000: 235-244 |
| 1999 |
|---|
| 2 | EE | Matt Postiff,
Gary S. Tyson,
Trevor N. Mudge:
Performance Limits of Trace Caches.
J. Instruction-Level Parallelism 1: (1999) |
| 1997 |
|---|
| 1 | | I-Cheng K. Chen,
Chih-Chieh Lee,
Matt Postiff,
Trevor N. Mudge:
Design Optimization for High-speed Per-address Two-level Branch Predictors.
ICCD 1997: 88-96 |
