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Matt Postiff

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2001
4EEMatt Postiff, David Greene, Steven E. Raasch, Trevor N. Mudge: Integrating superscalar processor components to implement register caching. ICS 2001: 348-357
2000
3EEMatt Postiff, David Greene, Trevor N. Mudge: The store-load address table and speculative register promotion. MICRO 2000: 235-244
1999
2EEMatt Postiff, Gary S. Tyson, Trevor N. Mudge: Performance Limits of Trace Caches. J. Instruction-Level Parallelism 1: (1999)
1997
1 I-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge: Design Optimization for High-speed Per-address Two-level Branch Predictors. ICCD 1997: 88-96

Coauthor Index

1I-Cheng K. Chen [1]
2David Greene [3] [4]
3Chih-Chieh Lee [1]
4Trevor N. Mudge [1] [2] [3] [4]
5Steven E. Raasch [4]
6Gary S. Tyson [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)