15. ISCA 1988:
Honolulu,
Hawaii,
USA
H. Siegel (Ed.):
Proceedings of the 15th Annual International Symposium on Computer Architecture. Honolulu,
Hawaii,
May-June 1988. IEEE Computer Society Press,
1988
- Joydeep Ghosh, Kai Hwang:
Critical Issues in Mapping Neural Networks on Message-Passing Multicomputers.
3-11 BibTeX
- Yoshiyasu Takefuji, Robert J. Jannarone, Yong B. Cho, Tatung Chen:
Multinomial Conjunctoid Statistical Learning Machines.
12-17 BibTeX
- Ahmed Louri, Kai Hwang:
A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution.
18-27 BibTeX
- Stuart Fiske, William J. Dally:
The Reconfigurable Arithmetic Processor.
30-36 BibTeX
- Andrew R. Pleszkun, Gurindar S. Sohi:
The Performance Potential of Multiple Functional Unit Processors.
37-44 BibTeX
- Wen-mei W. Hwu, Pohua P. Chang:
Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator.
45-53 BibTeX
- Geoffrey D. McNiven, Edward S. Davidson:
Analysis of Memory Referencing Behavior For Design of Local Memories.
56-63 BibTeX
- Richard J. Eickemeyer, Janak H. Patel:
Performance Evaluation of On-Chip Register and Cache Organizations.
64-72 BibTeX
- Jean-Loup Baer, Wen-Hann Wang:
On the Inclusion Properties for Multi-Level Cache Hierarchies.
73-80 BibTeX
- Robert T. Short, Henry M. Levy:
A Simulation Study of Two-Level Caches.
81-88 BibTeX
- E. Chow, H. Madan, J. Peterson, Dirk Grunwald, Daniel A. Reed:
Hyperswitch Network for the Hypercube Computer.
90-99 BibTeX
- Donald C. Winsor, Trevor N. Mudge:
Analysis of Bus Hierarchies for Multiprocessors.
100-107 BibTeX
- Sizheng Wei, Gyungho Lee:
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network.
108-115 BibTeX
- Hong Jiang, Kenneth C. Smith:
A Partial-Multiple-Bus Computer Structure with Improved Cost-Effectiveness.
116-122 BibTeX
- Ian Watson, Viv Woods, Paul Watson, Richard Banach, Mark Greenberg, John Sargeant:
Flagship: A Parallel Architecture for Declarative Programming.
124-130 BibTeX
- Robert A. Iannucci:
Toward a Dataflow/von Neumann Hybrid Architecture.
131-140 BibTeX
- David E. Culler, Arvind:
Resource Requirements of Dataflow Programs.
141-150 BibTeX
- Brinkley Sprunt, David Kirk, Lui Sha:
Priority-Driven, Preemptive I/O Controllers for Real-Time Systems.
152-159 BibTeX
- Shridhar B. Shukla, Dharma P. Agrawal:
A Kernel-independent, Pipelined Architecture for Real-Time 2-D Convolution.
160-166 BibTeX
- Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III:
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.
167-174 BibTeX
- Douglas W. Clark, Peter J. Bannon, James B. Keller:
Measuring VAX 8800 Performance with a Histogram Hardware Monitor.
176-185 BibTeX
- Richard L. Sites, Anant Agarwal:
Multiprocessor Cache Analysis Using ATUM.
186-195 BibTeX
- Spencer W. Ng, Dorothy Lang, Robert Selinger:
Trade-offs Between Devices and Paths in Achieving Disk Interleaving.
196-201 BibTeX
- K. Jainandunsing, Ed F. Deprettere:
Design of a Concurrent Computer for Solving Systems of Linear Equations.
204-211 BibTeX
- Andrew Wolfe, Mauricio Breternitz Jr., Chriss Stephens, A. L. Ting, D. B. Kirk, Ronald P. Bianchini Jr., John Paul Shen:
The White Dwarf: A High-Performance Application-Specific Processor.
212-222 BibTeX
- Jean-Luc Gaudiot, C. M. Lin, M. Hosseiniyar:
Solving Partial Differential Equations in a Data-Driven Multiprocessor Environment.
223-230 BibTeX
- De-Lei Lee:
Scrambled Storage for Parallel Memory Systems.
232-239 BibTeX
- Venkatesh Krishnaswamy, Sudhir Ahuja, Nicholas Carriero, David Gelernter:
The Architecture of a Linda Coprocessor.
240-249 BibTeX
- H. T. Kung:
Deadlock Avoidance for Systolic Communication.
252-260 BibTeX
- Kimming So, Vittorio Zecca:
Cache Performance of Vector Processors.
261-268 BibTeX
- Mary K. Vernon, Udi Manber:
Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration.
269-277 BibTeX
- Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz:
An Evaluation of Directory Schemes for Cache Coherence.
280-289 BibTeX
- Steven A. Przybylski, Mark Horowitz, John L. Hennessy:
Performance Tradeoffs in Cache Design.
290-298 BibTeX
- Hoichi Cheong, Alexander V. Veidenbaum:
A Cache Coherence Scheme With Fast Selective Invalidation.
299-307 BibTeX
- Mary K. Vernon, Edward D. Lazowska, John Zahorjan:
An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols.
308-315 BibTeX
- Darwen Rau, José A. B. Fortes, Howard Jay Siegel:
Destination Tag Routing Techniques Based on a State Model for the IADM Network.
318-324 BibTeX
- Doug W. Kim, G. Jack Lipovski, Alfred C. Hartmann, Roy M. Jenevein:
Regular CC-Banyan Networks.
325-332 BibTeX
- Roy M. Jenevein, Thomas Mookken:
Traffic Analysis of Rectangular SW-Banyan Networks.
333-342 BibTeX
- Yuval Tamir, Gregory L. Frazier:
High-Performance Multi-Queue Buffers for VLSI Communication Switches.
343-354 BibTeX
- Bruno R. Preiss, V. Carl Hamacher:
A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor.
358-364 BibTeX
- Taisuke Boku, Shigehiro Nomura, Hideharu Amano:
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation.
365-372 BibTeX
- Susan J. Eggers, Randy H. Katz:
A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation.
373-382 BibTeX
- G. Jack Lipovski, Paul Vaughan:
A Fetch-And-Op Implementation for Parallel Computers.
384-392 BibTeX
- André Seznec, Yvon Jégou:
Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor.
393-400 BibTeX
- Richard Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan:
Design and Performance of Special Purpose Hardware for Time Warp.
401-408 BibTeX
- David R. Cheriton, Anoop Gupta, Patrick D. Boyle, Hendrik A. Goosen:
The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation.
410-421 BibTeX
- James R. Goodman, Philip J. Woest:
The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor.
422-431 BibTeX
- Evan Tick:
Data Buffer Performance for Sequential Prolog Architectures.
434-442 BibTeX
- Robert H. Halstead Jr., Tetsuya Fujita:
MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing.
443-451 BibTeX
- Philip L. Butler, J. D. Allen Jr., Donald W. Bouldin:
Parallel Architecture for OPS5.
452-457 BibTeX
Copyright © Sat May 16 23:24:56 2009
by Michael Ley (ley@uni-trier.de)
