Volume 33,
Number 1 ,
March 2005
Special issue:
Workshop on architectural support for security and anti-virus (WASSA) Workshop on architectural support for security and anti-virus (WASSA)
- David M. Chess:
Security in autonomic computing.
2-5
Electronic Edition (ACM DL) BibTeX
- Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Mrinmoy Ghosh:
Towards the issues in architectural support for protection of software execution.
6-15
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- John Patrick McGregor, Ruby B. Lee:
Protecting cryptographic keys and computations via virtual secure coprocessing.
16-26
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- Brian Rogers, Yan Solihin, Milos Prvulovic:
Memory predecryption: hiding the latency overhead of memory encryption.
27-33
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- David A. Holland, Ada T. Lim, Margo I. Seltzer:
An architecture a day keeps the hacker away.
34-41
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- Stelios Sidiroglou, Michael E. Locasto, Angelos D. Keromytis:
Hardware support for self-healing software services.
42-47
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- Jedidiah R. Crandall, Frederic T. Chong:
A security assessment of the minos architecture.
48-57
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- Matthew Burnside, Angelos D. Keromytis:
The case for crypto protocol awareness inside the OS kernel.
58-64
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- Marc L. Corliss, E. Christopher Lewis, Amir Roth:
Using DISE to protect return addresses from attack.
65-72
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- Dong Ye, David R. Kaeli:
A reliable return address stack: microarchitectural features to defeat stack smashing.
73-80
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- Koji Inoue:
Energy-security tradeoff in a secure cache architecture against buffer overflow attacks.
81-89
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- Derek Uluski, Micha Moffie, David R. Kaeli:
Characterizing antivirus workload execution.
90-98
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- Monther Aldwairi, Thomas M. Conte, Paul D. Franzon:
Configurable string matching hardware for speeding up intrusion detection.
99-107
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- Milena Milenkovic, Aleksandar Milenkovic, Emil Jovanov:
Using instruction block signatures to counter code injection attacks.
108-117
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- Youtao Zhang, Jun Yang, Yongjing Lin, Lan Gao:
Architectural support for protecting user privacy on trusted processors.
118-123
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- Masaaki Shirase, Yasushi Hibino:
An architecture for elliptic curve cryptograph computation.
124-133
Electronic Edition (ACM DL) BibTeX
- Taeho Kgil, Laura Falk, Trevor N. Mudge:
ChipLock: support for secure microarchitectures.
134-143
Electronic Edition (ACM DL) BibTeX
Regular contributions
Internet nuggets
Volume 33,
Number 2,
May 2005
32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA.
IEEE Computer Society 2005
Contents BibTeX
Volume 33,
Number 3,
June 2005
MEDEA 2004 workshop
- Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Guests editor's introduction.
1-2
Electronic Edition (ACM DL) BibTeX
- Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin:
Energy aware memory architecture configuration.
3-9
Electronic Edition (ACM DL) BibTeX
- Hyo-Joong Suh, Sung Woo Chung:
DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency.
10-16
Electronic Edition (ACM DL) BibTeX
- Sami Yehia, Jean-Francois Collard, Olivier Temam:
Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.
17-24
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- Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa:
Locality analysis to control dynamically way-adaptable caches.
25-32
Electronic Edition (ACM DL) BibTeX
- Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori:
SH-X: an embedded processor core for consumer appliances.
33-40
Electronic Edition (ACM DL) BibTeX
- Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany:
Improving data cache performance with integrated use of split caches, victim cache and stream buffers.
41-48
Electronic Edition (ACM DL) BibTeX
- Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency.
49-56
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- Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications.
57-62
Electronic Edition (ACM DL) BibTeX
Regular contributions
Internet nuggets
Volume 33,
Number 4 ,
November 2005
Special issue:
dasCMP'05
- Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).
4
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- James Laudon:
Performance/Watt: the new server focus.
5-13
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- John D. Davis, Cong Fu, James Laudon:
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors.
14-23
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- Lisa R. Hsu, Ravishankar R. Iyer, Srihari Makineni, Steven K. Reinhardt, Donald Newell:
Exploring the cache design space for large scale CMPs.
24-33
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- John D. Davis, Stephen E. Richardson, Charis Charitsis, Kunle Olukotun:
A chip prototyping substrate: the flexible architecture for simulation and testing (FAST).
34-43
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- Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors:
Chip multi-processor scalability for single-threaded applications.
44-53
Electronic Edition (ACM DL) BibTeX
- Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi:
Hardware-modulated parallelism in chip multiprocessors.
54-63
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- Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker:
Fast synchronization for chip multiprocessors.
64-69
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- Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood:
Dynamically configurable shared CMP helper engines for improved performance.
70-79
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- Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec:
Performance implications of single thread migration on a chip multi-core.
80-91
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Regular contributions
- Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood:
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.
92-99
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- David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob:
DRAMsim: a memory system simulator.
100-107
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- Barry Rountree, Robert Springer, David K. Lowenthal, Vincent W. Freeh:
Notes from HPPAC 2005.
108-112
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- H. C. Wang, C. K. Yuen:
A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware.
113-120
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- Nana B. Sam, Martin Burtscher:
Improving memory system performance with energy-efficient value speculation.
121-127
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Departments
Copyright © Sun May 17 00:19:07 2009
by Michael Ley (ley@uni-trier.de)
